ATMEGA8515-16MU Atmel, ATMEGA8515-16MU Datasheet



Manufacturer Part Number
AVR® ATmegar

Specifications of ATMEGA8515-16MU

Core Processor
Core Size
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
8KB (4K x 16)
Program Memory Type
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
3rd Party Development Tools
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
For Use With
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
Lead Free Status / Rohs Status
High-performance, Low-power AVR
RISC Architecture
Nonvolatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 8K Bytes of In-System Self-programmable Flash
– Optional Boot Code Section with Independent Lock bits
– 512 Bytes EEPROM
– 512 Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Three PWM Channels
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power-down and Standby
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
– 2.7 - 5.5V for ATmega8515L
– 4.5 - 5.5V for ATmega8515
– 0 - 8 MHz for ATmega8515L
– 0 - 16 MHz for ATmega8515
Endurance: 10,000 Write/Erase Cycles
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Endurance: 100,000 Write/Erase Cycles
8-bit Microcontroller
Note: This is a summary document. A complete document
is available on our Web site at
with 8K Bytes

Related parts for ATMEGA8515-16MU

ATMEGA8515-16MU Summary of contents

Page 1

... Operating Voltages – 2.7 - 5.5V for ATmega8515L – 4.5 - 5.5V for ATmega8515 • Speed Grades – MHz for ATmega8515L – MHz for ATmega8515 ® 8-bit Microcontroller Note: This is a summary document. A complete document is available on our Web site at 8-bit Microcontroller ...

Page 2

... Pin Configurations Figure 1. Pinout ATmega8515 TQFP/MLF (MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3 RESET 4 (RXD) PD0 5 NC* 6 (TXD) PD1 7 (INT0) PD2 8 (INT1) PD3 9 (XCK) PD4 10 (OC1A) PD5 11 ATmega8515(L) 2 PDIP (OC0/T0) PB0 1 40 VCC (T1) PB1 2 39 PA0 (AD0) (AIN0) PB2 3 38 PA1 (AD1) ...

Page 3

... Overview Block Diagram 2512JS–AVR–10/06 The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. ...

Page 4

... In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8515 is supported with a full suite of program and system development tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-cir- cuit Emulators, and Evaluation kits. ...

Page 5

... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega8515 as listed on page 74. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...

Page 6

... Resources ATmega8515( comprehensive set of development tools, application notes and datasheets are avail- able for download on 2512JS–AVR–10/06 ...

Page 7

... These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit defini- tions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documentation for more details. ATmega8515(L) 7 ...

Page 8

... DDRE - $05 ($25) PINE - $04 ($24) OSCCAL Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. ATmega8515(L) 8 Bit 6 Bit 5 Bit 4 Bit SP14 ...

Page 9

... Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 2512JS–AVR–10/06 ATmega8515(L) 9 ...

Page 10

... Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled ATmega8515(L) 10 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 11

... Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS 2512JS–AVR–10/06 ATmega8515(L) Operation Flags Rd ← Rr None Rd+1:Rd ← Rr+1:Rr None Rd ← K None Rd ← (X) None Rd ← ...

Page 12

... Description Mnemonics Operands NOP No Operation SLEEP Sleep WDR Watchdog Reset ATmega8515(L) 12 Operation Flags None (see specific descr. for Sleep function) None (see specific descr. for WDR/timer) None #Clocks 2512JS–AVR–10/06 ...

Page 13

... ATmega8515-16MC 44M1 ATmega8515-16AI 44A ATmega8515-16PI 40P6 ATmega8515-16JI 44J ATmega8515-16MI 44M1 (2) ATmega8515-16AU 44A (2) ATmega8515-16PU 40P6 (2) ATmega8515-16JU 44J (2) ATmega8515-16MU 44MI Package Type ATmega8515(L) (1) Operation Range Commercial 0°C to 70°C) ( Industrial 0°C to 85°C) (-4 Commercial 0°C to 70°C) ( Industrial 0°C to 85°C) (-4 13 ...

Page 14

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega8515( PIN 1 IDENTIFIER ...

Page 15

... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2512JS–AVR–10/06 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) ATmega8515(L) E1 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A – – 4.826 A1 0.381 – – D 52.070 – ...

Page 16

... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega8515(L) 16 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

Page 17

... Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega8515(L) SEATING PLANE SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A 0.80 ...

Page 18

... ATmega8515(L) Rev. C and D ATmega8515(L) 18 The revision letter in this section refers to the revision of the ATmega8515 device. 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conver- sion will take longer than expected on some devices. ...

Page 19

... Updated Table 18 on page 46 and “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical Characteristics” on page 197. 3. Updated chapter “ATmega8515 Typical Characteristics” on page 207. 1. Added “EEPROM Write During Power-down Sleep Mode” on page 23. 2. Improved the description in “Phase Correct PWM Mode” on page 88. ...

Page 20

... Rev. 2512C-10/02 Rev. 2512B-09/02 Rev. 2512A-04/02 ATmega8515( Added “Using all Locations of External Memory Smaller than 64 KB” on page 31. 2. Removed all TBD. 3. Added description about calibration values for 2, 4, and 8 MHz. 4. Added variation in frequency of “External Clock” on page 40. 5. Added note about V , Table 18 on page 46 ...

Page 21

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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