ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 210

• Manufacturer Part Number: ATMEGA88-20MUR
• Description: MCU AVR 8K FLASH 20MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88-20MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: MLF EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.2.2
22.3
22.3.1
22.3.2
2545T–AVR–05/11
Data transfer and frame format
Electrical interconnection
Transferring bits
START and STOP conditions
Table 22-1.
The PRTWI bit in
the 2-wire serial interface.
As depicted in
age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or
open-collector. This implements a wired-AND function which is essential to the operation of the
interface. A low level on a TWI bus line is generated when one or more TWI devices output a
zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resis-
tors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical charac-
teristics of the TWI is given in
sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one
valid for bus speeds up to 400kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 22-2. Data validity.
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
Term
Slave
Transmitter
Receiver
SDA
SCL
TWI terminology.
Figure 22-1 on page
Description
The device addressed by a master.
The device placing data on the bus.
The device reading data from the bus.
“Minimizing power consumption” on page 41
“2-wire serial interface characteristics” on page
Data stable
209, both bus lines are connected to the positive supply volt-
Data change
Data stable
ATmega48/88/168
must be written to zero to enable
308. Two different
210