PIC16LC716-04I/P Microchip Technology, PIC16LC716-04I/P Datasheet - Page 31
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PIC16LC716-04I/P
Manufacturer Part Number
PIC16LC716-04I/P
Description
IC MCU OTP 2KX14 A/D PWM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16C716-04P.pdf
(106 pages)
Specifications of PIC16LC716-04I/P
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
13
Number Of Timers
3 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
4 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
4.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the
(DS33023).
4.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
Timer0
(OPTION_REG<4>). Clearing bit T0SE selects the
rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
FIGURE 4-1:
© 2005 Microchip Technology Inc.
RA4/T0CKI
pin
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
PICmicro
TIMER0 MODULE
Timer0 Operation
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
Source
T0SE
OSC
®
F
). Also, there is a delay in the actual
OSC
(1)
Mid-Range
Edge
TIMER0 BLOCK DIAGRAM
/4
T0CS
Select
Reference
0
1
(1)
PS2, PS1, PS0
bit
Programmable
Prescaler
Manual,
T0SE
3
(2)
(1)
PSA
1
0
(1)
Additional information on external clock requirements
is available in the PICmicro
Manual, (DS33023).
4.2
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available, which is mutually exclusively shared
between the Timer0 module and the Watchdog Timer.
Thus, a prescaler assignment for the Timer0 module
means that there is no prescaler for the Watchdog
Timer and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
PSout
Note:
(2-cycle delay)
1,x....etc.) will clear the prescaler. When
Sync with
Prescaler
Internal
clocks
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
PIC16C712/716
PSout
Data Bus
®
TMR0
Mid-Range Reference
8
DS41106B-page 29
Set Interrupt
Flag bit T0IF
on overflow