PIC16C717-I/SO Microchip Technology, PIC16C717-I/SO Datasheet
PIC16C717-I/SO
Specifications of PIC16C717-I/SO
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PIC16C717-I/SO Summary of contents
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... CMOS Microcontrollers 2002 Microchip Technology Inc. M PIC16C717/770/771 Data Sheet with 10/12-bit A/D DS41120B ...
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... Serialized Quick Term Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... PWM max. resolution is 10-bit - Enhanced PWM: - Single, Half-Bridge and Full-Bridge Output modes - Digitally programmable deadband delay • Analog-to-Digital converter: - PIC16C770/771 12-bit resolution - PIC16C717 10-bit resolution • On-chip absolute bandgap voltage reference generator • Programmable Brown-out Reset (PBOR) circuitry • Programmable Low-Voltage Detection (PLVD) circuitry • ...
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... RA5/MCLR/V PP RA6/OSC2/CLKOUT ( ( RB7/T1OSI/P1D RA2/AN2/V -/VRL REF RB6/T1OSO/T1CKI/P1C RA3/AN3/V +/VRH REF RB5/SDO/P1B RB0/AN4/INT RB4/SDI/SDA RB1/AN5/SS PIC16C717 PIC16C770 MHz MHz POR, BOR, MCLR, POR, BOR, MCLR, WDT (PWRT, OST) WDT (PWRT, OST 256 256 10 10 Ports A,B Ports A MSSP MSSP – 6 input channels 6 input channels – ...
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... Index .......................................................................................................................................................................... 209 On-Line Support.......................................................................................................................................................... 215 Reader Response ....................................................................................................................................................... 216 PIC16C717/770/771 Product Identification System .................................................................................................... 217 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... PIC16C717/770/771 NOTES: DS41120B-page 4 2002 Microchip Technology Inc. ...
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... TM There are three devices (PIC16C717, PIC16C770 and Manual, PIC16C771) covered by this data sheet. The PIC16C717 device comes in 18/20-pin packages and the PIC16C770/771 devices come in 20-pin packages. The following two figures are device block diagrams of the PIC16C717 and the PIC16C770/771. 8 ...
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... PIC16C717/770/771 FIGURE 1-2: PIC16C770/771 BLOCK DIAGRAM 13 Program Counter EPROM Program (2) Memory 8 Level Stack Program 14 Program Memory Bus Read (PMR) Instruction reg Direct Addr Internal 4 MHz, 37 kHz and ER mode Instruction Decode & Power-up Control Timing Oscillator Generation Start-up Timer OSC1/CLKIN Power-on OSC2/CLKOUT ...
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... TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION Name Function RA0 RA0/AN0 AN0 RA1 RA1/AN1/LVDIN AN1 LVDIN RA2 AN2 RA2/AN2/V -/VRL REF V - REF VRL RA3 AN3 RA3/AN3/V +/VRH REF V + REF VRH RA4 RA4/T0CKI T0CKI RA5 RA5/MCLR/V MCLR RA6 RA6/OSC2/CLKOUT OSC2 CLKOUT RA7 RA7/OSC1/CLKIN OSC1 ...
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... PIC16C717/770/771 TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION (CONTINUED) Name Function RB6 T1OSO RB6/T1OSO/T1CKI/P1C T1CKI P1C RB7 RB7/T1OSI/P1D T1OSI P1D ( ( Note 1: Bit programmable pull-ups. 2: Only in PIC16C770/771 devices. DS41120B-page 8 Input Output Type Type (1) TTL CMOS Bi-directional I/O XTAL Crystal/Resonator CMOS TMR1 clock input CMOS ...
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... PICmicro Mid-Range MCU Family Reference Manual, (DS33023). 2.1 Program Memory Organization The PIC16C717/770/771 devices have a 13-bit pro- gram counter capable of addressing pro- gram memory space. The PIC16C717 and the PIC16C770 have words of program memory. The PIC16C771 has words of program mem- ory ...
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... PIC16C717/770/771 FIGURE 2-3: REGISTER FILE MAP File Address (*) Indirect addr. 00h Indirect addr. 01h TMR0 OPTION_REG PCL 02h STATUS 03h 04h FSR 05h PORTA PORTB 06h 07h 08h 09h PCLATH 0Ah 0Bh INTCON PIR1 0Ch 0Dh PIR2 0Eh TMR1L 0Fh TMR1H ...
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... The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bank 0 (3) ...
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... PIC16C717/770/771 TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (3) 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RBPU INTEDG (3) 82h PCL Program Counter’s (PC) Least Significant Byte ...
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... TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 2 (3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 100h 101h TMR0 Timer0 module’s register (3) PCL Program Counter's (PC) Least Significant Byte 102h ...
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... PIC16C717/770/771 2.2.2.1 STATUS REGISTER The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS ...
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... Note 1: Individual weak pull- pins can be enabled/disabled from the weak pull-up PORTB Register (WPUB). Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 ...
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... PIC16C717/770/771 2.2.2.3 INTCON REGISTER The INTCON Register is a readable and writable regis- ter, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh) ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 U-0 R/W-0 ADIE — ...
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... PIC16C717/770/771 2.2.2.5 PIR1 REGISTER This register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch) U-0 R/W-0 — ADIF bit 7 bit 7 Unimplemented: Read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit A/D conversion completed ...
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... BCLIE: Bus Collision Interrupt Enable bit 1 = Bus Collision interrupt is enabled 0 = Bus Collision interrupt is disabled bit 2-0 Unimplemented: Read as '0' Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 U-0 U-0 U-0 R/W-0 — — — BCLIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PIC16C717/770/771 2.2.2.7 PIR2 REGISTER This register contains the SSP Bus Collision and low- voltage detect interrupt flag bits. REGISTER 2-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh) R/W-0 LVDIF bit 7 bit 7 LVDIF: Low Voltage Detect Interrupt Flag bit 1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software) ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. ...
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... All updates to the PCH register occur through the PCLATH register. 2.3.1 PROGRAM MEMORY PAGING PIC16C717/770/771 devices are capable of address- ing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page ...
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... RP1:RP0 6 from opcode bank select location select 00h Data Memory(1) 7Fh Bank 0 Note 1: For register file map detail see Figure 2-3. 2002 Microchip Technology Inc. PIC16C717/770/771 EXAMPLE 2-1: movlw movwf NEXT clrf incf btfss goto CONTINUE : An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS< ...
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... PIC16C717/770/771 NOTES: DS41120B-page 24 2002 Microchip Technology Inc. ...
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... PICmicro™ Mid-Range MCU Family Reference Man- ual, (DS33023). 3.1 I/O Port Analog/Digital Mode The PIC16C717/770/771 have two I/O ports: PORTA and PORTB. Some of these port pins are mixed-signal (can be digital or analog). When an analog signal is REGISTER 3-1: ANALOG SELECT REGISTER (ANSEL: 9Dh) ...
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... PIC16C717/770/771 EXAMPLE 3-1: Initializing PORTA BCF STATUS, RP0 ; Select Bank 0 CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0Fh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<7:4> as outputs. RA<7:6>availability depends on oscillator selection. ...
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... Bus WR PORT TRIS Mode WR TRIS RD TRIS Analog Select WR ANSEL RD PORT To A/D Converter input and inputs REF REF (From V VRH, VRL output enable 2002 Microchip Technology Inc. PIC16C717/770/771 -/VRL AND RA3/AN3/V REF Data Latch VRH, VRL outputs -LVD-BOR Module) REF Sense input for ...
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... PIC16C717/770/771 FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI Data Latch Data Bus D WR Port CK TRIS Latch D WR TRIS CK RD TRIS RD PORT TMR0 clock input DS41120B-page Schmitt Trigger Input Buffer 2002 Microchip Technology Inc. ...
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... FIGURE 3-4: BLOCK DIAGRAM OF RA5/MCLR/V To MCLR Circuit Program Mode Data Bus RD TRIS RD PORT 2002 Microchip Technology Inc. PIC16C717/770/771 PP MCLR Filter HV Detect V SS Schmitt Trigger DS41120B-page 29 ...
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... PIC16C717/770/771 FIGURE 3-5: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN (INTRC or ER) and CLKOUT CLKOUT (Fosc/ Data D Q Bus PORTA Data Latch TRISA TRIS Latch RD TRISA Q RD PORTA DS41120B-page 30 From OSC1 Oscillator Circuit [(ER or INTRC) and CLKOUT Schmitt Trigger Input Buffer 2002 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN Data D Q Bus PORTA Data Latch TRISA TRIS Latch INTRC RD TRISA Q RD PORTA 2002 Microchip Technology Inc. PIC16C717/770/771 To OSC2 Oscillator To Chip Clock Drivers Schmitt Trigger Vss D EN Circuit V DD Input Buffer EC Mode INTRC Schmitt Trigger Input Buffer DS41120B-page 31 ...
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... PIC16C717/770/771 TABLE 3-1: PORTA FUNCTIONS Name Function RA0 RA0/AN0 AN0 RA1 RA1/AN1/LVDIN AN1 LVDIN RA2 AN2 RA2/AN2/V -/VRL REF V - REF VRL RA3 AN3 RA3/AN3/V +/VRH REF V + REF VRH RA4 RA4/T0CKI T0CKI RA5 RA5/MCLR/V MCLR RA6 RA6/OSC2/CLKOUT OSC2 CLKOUT RA7 RA7/OSC1/CLKIN OSC1 ...
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... The pull-ups are disabled on a Power-on Reset. 2002 Microchip Technology Inc. PIC16C717/770/771 Each of the PORTB pins, if configured as input, also has an interrupt-on-change feature, which can be indi- vidually selected from the IOCB register. The RBIE bit in the INTCON register functions as a global enable bit to turn on/off the interrupt-on-change feature ...
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... PIC16C717/770/771 REGISTER 3-2: WEAK PULL-UP PORTB REGISTER (WPUB: 95h) R/W-1 R/W-1 WPUB7 WPUB6 bit 7 bit 7-0 WPUB<7:0>: PORTB Weak Pull-Up Control bits 1 = Weak pull-up enabled 0 = Weak pull-up disabled Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG register must be cleared ...
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... PORT To INT input or MSSP module To A/D Converter 2002 Microchip Technology Inc. PIC16C717/770/771 The RB1 pin is multiplexed with the A/D converter ana- log input 5 and the MSSP module slave select input (RB1/AN5/SS). When the pin is used as analog input, the ANSEL register must have the proper value to select the RB1 pin as Analog mode ...
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... PIC16C717/770/771 FIGURE 3-8: BLOCK DIAGRAM OF RB2/SCK/SCL, RB3/CCP1/P1A, RB4/SDI/SDA, RB5/SDO/P1B WPUB Reg Data Bus WPUB CK Q Spec. Func En. SDA, SDO, SCK, CCP1, P1A, P1B PORTB Reg PORT CK Q TRIS Reg TRIS TRIS IOCB Reg IOCB PORT SCK, SCL, CC, SDI, SDA inputs DS41120B-page 36 ...
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... Q WR IOCB CK Q TMR1 Clock Serial programming clock From RB7 Set RBIF From RB<7:0> pins Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions. 2002 Microchip Technology Inc. PIC16C717/770/771 Q RBPU CMOS Schmitt Trigger TMR1 Oscillator V DD ...
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... PIC16C717/770/771 FIGURE 3-10: BLOCK DIAGRAM OF THE RB7/T1OSI/P1D RBPU WPUB Reg Data Bus D WR WPUB PORTB CK Data Latch D WR TRISB TRIS Latch RD TRISB T10SCEN RD PORTB IOCB Reg D WR IOCB CK Serial programming input Schmitt Trigger Set RBIF Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB7 I/O port and P1D functions. ...
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... WPUB PORTB Weak Pull-up Control 96h IOCB PORTB Interrupt on Change Control 9Dh ANSEL — — Legend unknown unchanged. Shaded cells are not used by PORTB. 2002 Microchip Technology Inc. PIC16C717/770/771 Input Output Type Type (1) TTL CMOS Bi-directional I/O AN A/D input ST Interrupt input ...
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... PIC16C717/770/771 NOTES: DS41120B-page 40 2002 Microchip Technology Inc. ...
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... PMADRH and PMADRL registers upon completion of a Program Memory Read command. 2002 Microchip Technology Inc. PIC16C717/770/771 When interfacing the program memory block, the PMDATH & PMDATL registers form a 2-byte word, which holds the 14-bit data. The PMADRH & PMADRL ...
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... PIC16C717/770/771 REGISTER 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh) U-0 — bit 7 bit 7-6 Unimplemented: Read as '0' bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a Program Memory Read command. Legend Readable bit - n = Value at POR ...
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... Executed here RD bit PMDATH PMDATL register 2002 Microchip Technology Inc. PIC16C717/770/771 the “ ” instruction to be ignored. The data BSF PMCON1,RD is available, in the very next cycle, in the PMDATH and PMDATL registers; therefore it can be read as 2 bytes in the following instructions. PMDATH and PMDATL ...
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... PIC16C717/770/771 TABLE 4-1: PROGRAM MEMORY READ REGISTER SUMMARY Address Name Bit 7 Bit 6 18Ch PMCON1 Reserved — 10Eh PMDATH — — 10Ch PMDATL PMD7 PMD6 10Fh PMADRH — — 10Dh PMADRL PMA7 PMA6 Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Program Memory Read. ...
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... T0CS Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram). 2002 Microchip Technology Inc. PIC16C717/770/771 Additional information on external clock requirements is available in the PICmicro™ Mid-Range MCU Family Reference Manual, (DS33023). 5.2 ...
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... PIC16C717/770/771 5.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “on-the-fly” during program execution). Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicro™ Mid-Range Reference Man- ual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT ...
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... Stops Timer1 Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual, (DS33023). 6.1 Timer1 Operation Timer1 can operate in one of these modes: • ...
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... PIC16C717/770/771 6.1.1 TIMER1 COUNTER OPERATION In this mode, Timer1 is being incremented via an exter- nal source. Increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 6-1: TIMER1 INCREMENTING EDGE ...
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... Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by the Timer1 module. 2002 Microchip Technology Inc. PIC16C717/770/771 6.3 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1< ...
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... PIC16C717/770/771 NOTES: DS41120B-page 50 2002 Microchip Technology Inc. ...
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... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 7.1 Timer2 Operation Timer2 can be used as the PWM time-base for PWM mode of the ECCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (F ...
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... PIC16C717/770/771 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. 7.3 ...
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... PWM mode. P1A, P1C active low. P1B, P1D active low. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON and P1DEL reg- isters control the operation of ECCP. All are readable and writable ...
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... PIC16C717/770/771 TABLE 8-1: ECCP MODE - TIMER RESOURCE ECCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 8.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16- bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as: • every falling edge • ...
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... PWM1M0 DC1B1 Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1. 2002 Microchip Technology Inc. PIC16C717/770/771 FIGURE 8-2: Special event trigger will: RESET Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>). Special Event Trigger ...
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... PIC16C717/770/771 8.3 PWM Mode In Pulse Width Modulation (PWM) mode, the ECCP module produces 10-bit resolution PWM output. Figure 8-3 shows the simplified PWM block diagram. FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty cycle registers CCPR1L CCPR1H (Slave) R Comparator (Note 1) TMR2 ...
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... PIC16C717/770/771 R CCP1 Vout C Using PWM to V+ Drive a Power Load PIC16C717/770/771 CCP1 In the Half-Bridge Output mode, two pins are used as outputs. The RB3/CCP1/P1A pin has the PWM output signal, while the RB5/SDO/P1B pin has the comple- mentary PWM output signal. This mode can be used ...
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... PIC16C717/770/771 8.3.4 OUTPUT POLARITY CONFIGURATION The CCP1M<1:0> bits in the CCP1CON register allow user to choose the logic conventions (asserted high/ low) for each of the outputs. See Register 8-1 for fur- ther details. FIGURE 8-6: HALF-BRIDGE PWM OUTPUT Period Period Duty Cycle P1A(2) ...
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... FIGURE 8-7: EXAMPLE OF HALF-BRIDGE OUTPUT MODE APPLICATIONS PIC16C717/770/771 P1A P1B PIC16C717/770/771 P1A P1B 2002 Microchip Technology Inc. PIC16C717/770/771 V+ FET DRIVER FET DRIVER V- V+ FET DRIVER + - LOAD FET DRIVER LOAD + V - FET DRIVER FET DRIVER DS41120B-page 59 ...
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... PIC16C717/770/771 In Full-Bridge Output mode, four pins are used as out- puts; however, only two outputs are active at a time. In the Forward mode, RB3/CCP1/P1A pin is continuously active, and RB7/T1OSI/P1D pin is modulated. In the Reverse mode, RB6/T1OSO/T1CKI/P1C pin is contin- uously active, and RB5/SDO/P1B pin is modulated. ...
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... FIGURE 8-9: EXAMPLE OF FULL-BRIDGE APPLICATION PIC16C717/770/771 P1D P1C P1A P1B 2002 Microchip Technology Inc. PIC16C717/770/771 V+ FET DRIVER + - LOAD FET DRIVER V- FET DRIVER FET DRIVER DS41120B-page 61 ...
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... PIC16C717/770/771 8.3.5 PROGRAMMABLE DEADBAND DELAY In half-bridge or full-bridge applications, driven by half- bridge outputs (see Figure 8-7), the power switches normally require longer time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches will be on for a short period of time, until one switch completely turns off ...
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... Microchip Technology Inc. PIC16C717/770/771 example, since the turn off time of the power devices is longer than the turn on time, a shoot-through current flows through the power devices, QB and QD, for the duration ...
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... PIC16C717/770/771 8.3.7 SYSTEM IMPLEMENTATION When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the PWM output pins. When the microcontroller powers up, all of the I/O pins are in the high-impedance state. The external pull-up ...
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... These peripheral devices may be serial EEPROMs, shift registers, dis- play drivers, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI™) 2 • Inter-Integrated Circuit (I C™) 2002 Microchip Technology Inc. PIC16C717/770/771 Advance Information DS41120B-page 65 ...
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... PIC16C717/770/771 REGISTER 9-1: SYNC SERIAL PORT STATUS REGISTER (SSPSTAT: 94h) R/W-0 R/W-0 SMP bit 7 bit 7 SMP: Sample bit SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in Slave mode ...
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... Holds clock low (clock stretch) (used to ensure data setup time Master mode Unused in this mode Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’ ...
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... PIC16C717/770/771 REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h) (CONTINUED) bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = F 0001 = SPI Master mode, clock = F 0010 = SPI Master mode, clock = F 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin ...
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... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 R/W-0 R/W-0 R/W-0 ACKDT ACKEN RCEN ...
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... PIC16C717/770/771 9.1 SPI Mode The SPI mode allows eight bits of data to be synchro- nously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish com- munication, typically three pins are used: • Serial Data Out (SDO) • Serial Data In (SDI) • ...
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... Shift Register (SSPSR) MSb PROCESSOR 1 2002 Microchip Technology Inc. PIC16C717/770/771 9.1.2 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON reg- isters, and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins ...
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... PIC16C717/770/771 9.1.4 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 9- broad- cast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI module is only going to receive, the SDO output could be disabled (programmed as an input) ...
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... Interrupt Flag SSPSR to SSPBUF 2002 Microchip Technology Inc. PIC16C717/770/771 SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desir- able, depending on the application. ...
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... PIC16C717/770/771 FIGURE 9-5: SPI SLAVE MODE WAVEFORM (CKE = 0) SS optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 9-6: SPI SLAVE MODE WAVEFORM (CKE = 1) SS not optional ...
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... ANSEL 86h TRISB Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode. 2002 Microchip Technology Inc. PIC16C717/770/771 9.1.8 EFFECTS OF A RESET A RESET disables the MSSP module and terminates the current transfer. Bit 5 Bit 4 ...
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... PIC16C717/770/771 2 9.2 MSSP I C Operation 2 The MSSP module mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on START and STOP bits in hardware to determine when the bus is free (multi- master function). The MSSP module implements the Standard mode specifications, as well as 7-bit and 10- bit addressing ...
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... SSP interrupt flag bit; SSPIF (PIR1<3>) is set (interrupt is generated if enabled the falling edge of the ninth SCL pulse. 2002 Microchip Technology Inc. PIC16C717/770/771 9.2.2.2 10-BIT ADDRESSING In 10-bit mode, the basic receive and transmit opera- tions are the same as in the 7-bit mode. However, the criteria for address match are more complex ...
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... PIC16C717/770/771 9.2.2.3 SLAVE RECEPTION When the R/W bit of the address byte is clear (SSPSR<0> and an address match occurs, the R/ W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register on the fall- ing edge of the eighth SCL pulse. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT< ...
Page 81
... FIGURE 9- SLAVE MODE FOR RECEPTION (10-BIT ADDRESS) 2002 Microchip Technology Inc. PIC16C717/770/771 Advance Information DS41120B-page 79 ...
Page 82
... PIC16C717/770/771 9.2.2.4 SLAVE TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSP- STAT register is set. The received address is loaded into the SSPBUF register on the falling edge of the eighth SCL pulse. The ACK pulse will be sent on the ninth bit, and the SCL pin is held low ...
Page 83
... I FIGURE 9-11: C SLAVE MODE WAVEFORMS FOR TRANSMISSION (10-BIT ADDRESS) 2002 Microchip Technology Inc. PIC16C717/770/771 Advance Information DS41120B-page 81 ...
Page 84
... PIC16C717/770/771 9.2.3 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the START condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
Page 85
... SDA SDA in SCL SCL in Bus Collision 2002 Microchip Technology Inc. PIC16C717/770/771 9.2.6 MASTER MODE Master mode operation supports interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control ...
Page 86
... PIC16C717/770/771 9.2.7 MULTI-MASTER OPERATION In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear ...
Page 87
... SDA line held low. • The SSPIF flag is set. FIGURE 9-16: FIRST START BIT TIMING Write to SEN bit occurs here. SDA SCL 2002 Microchip Technology Inc. PIC16C717/770/771 DX-1 SCL allowed to transition high BRG decrements (on Q2 and Q4 cycles) 02h 01h 00h (hold off) SCL is sampled high, reload takes place, and BRG starts its count ...
Page 88
... PIC16C717/770/771 2 9.2. MASTER MODE REPEATED START CONDITION TIMING A Repeated START condition occurs when the RSEN bit (SSPCON2<1>) is set high while the I in the idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD< ...
Page 89
... SSPBUF leaving SCL low and SDA unchanged (Figure 9-18). 2002 Microchip Technology Inc. PIC16C717/770/771 A typical transmit sequence would go as follows: a) The user generates a START Condition by set- ting the START enable bit (SEN) in SSPCON2. ...
Page 90
... PIC16C717/770/771 2 FIGURE 9-18 MASTER MODE WAVEFORMS FOR TRANSMISSION (7 OR 10-BIT ADDRESS) DS41120B-page 88 Advance Information 2002 Microchip Technology Inc. ...
Page 91
... Acknowledge bit at the end of reception by clearing the ACKDT bit (SSPCON2<5>) and setting the Acknowl- edge sequence enable bit, ACKEN (SSPCON2<4>). 2002 Microchip Technology Inc. PIC16C717/770/771 A typical receive sequence would go as follows: a) The user generates a START Condition by set- ting the START enable bit (SEN) in SSPCON2. ...
Page 92
... PIC16C717/770/771 2 FIGURE 9-19 MASTER WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) DS41120B-page 90 Advance Information 2002 Microchip Technology Inc. ...
Page 93
... SSPIF occurs at the end of receive Note one baud rate generator period. BRG 2002 Microchip Technology Inc. PIC16C717/770/771 arbitration), the baud rate generator is reloaded and counts for another T period, the following events occur (see Figure 9-20): • The SCL pin is pulled low. bit, ACKEN • ...
Page 94
... PIC16C717/770/771 9.2.15 STOP CONDITION TIMING The master asserts a STOP condition on the SDA and SCL pins at the end of a receive/transmit by setting the Stop Sequence Enable bit PEN (SSPCON2<2>). At the end of a receive/transmit plus Acknowledge, the SCL line is held low immediately following the falling edge of the ninth SCL pulse ...
Page 95
... SCL SDA T BRG 2002 Microchip Technology Inc. PIC16C717/770/771 SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 9-22) ...
Page 96
... PIC16C717/770/771 9.2.17 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, bus arbitration is initiated when one mas- ter outputs a ’1’ on SDA (by letting SDA float high) and another master asserts a ’ ...
Page 97
... BCLIF SDA = 0, SCL = 1 S SSPIF 2002 Microchip Technology Inc. PIC16C717/770/771 while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ’1’ during the START condition. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 9-26). If however a ’ ...
Page 98
... PIC16C717/770/771 FIGURE 9-25: BUS COLLISION DURING START CONDITION (SCL = 0) SDA Set SEN, enable START SCL sequence if SDA = 1, SCL = 1 SEN SCL = 0 before BRG time out, Bus collision occurs, Set BCLIF. BCLIF S ’0’ ’0’ SSPIF FIGURE 9-26: BRG RESET DUE TO SDA COLLISION DURING START CONDITION Less than T SDA pulled low by other master ...
Page 99
... S ’0’ SSPIF 2002 Microchip Technology Inc. PIC16C717/770/771 ’0’). If however SDA is sampled high, then the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time ...
Page 100
... PIC16C717/770/771 9.2.17.3 BUS COLLISION DURING A STOP CONDITION Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. b) After the SCL pin is de-asserted, SCL is sam- pled low before SDA goes high ...
Page 101
... ACKSTAT 94h SSPSTAT SMP CKE 93h SSPADD Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the MSSP in I 2002 Microchip Technology Inc. PIC16C717/770/771 example, with a supply voltage max = function The desired noise margin of 0.1V limits the maximum value of R optional and used to improve ESD susceptibility ...
Page 102
... PIC16C717/770/771 NOTES: DS41120B-page 100 Advance Information 2002 Microchip Technology Inc. ...
Page 103
... Selection of reserved setting may result in an inadvertent interrupt. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC16C717/770/771 The source for the reference voltages comes from the bandgap reference circuit. The bandgap circuit is ener- gized anytime the reference voltage is required by the other sub-modules, and is powered down when not in use ...
Page 104
... PIC16C717/770/771 REGISTER 10-2: VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 9BH) R/W-0 R/W-0 VRHEN VRLEN bit 7 bit 7 VRHEN: Voltage Reference High Enable bit (VRH = 4.096V nominal Enabled, powers up reference generator 0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL bit 6 VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V nominal) ...
Page 105
... V DD RA1/AN1/LVDIN LVDEN 2002 Microchip Technology Inc. PIC16C717/770/771 The VRL reference is enabled by setting control bit VRLEN (REFCON<6>). When this bit is set, the gain amplifier is enabled. After a specified start-up time a stable reference of 2.048V nominal is generated and can be used by the A/D converter as a reference input. ...
Page 106
... PIC16C717/770/771 10.3 Low Voltage Detect (LVD) This module is used to generate an interrupt when the supply voltage falls below a specified “trip” voltage. This module operates completely under software control. This allows a user to power the module on and off to periodically monitor the supply voltage, and thus minimize total current consumption ...
Page 107
... CONVERTER (A/D) MODULE The analog-to-digital (A/D) converter module has six inputs for the PIC16C717/770/771. The PIC16C717 analog-to-digital converter (A/D) allows conversion of an analog input signal to a corre- sponding 10-bit digital value, while the A/D converter in the PIC16C770/771 allows conversion to a corre- sponding 12-bit digital value ...
Page 108
... PIC16C717/770/771 REGISTER 11-1: A/D CONTROL REGISTER 0 (ADCON0: 1Fh). R/W-0 R/W-0 ADCS1 ADCS0 bit 7 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits If internal VRL and/or VRH are not used for A/D reference (VCFG<2:0> = 000, 001, 011 or 101 OSC OSC /32 OSC (clock derived from a dedicated RC oscillator internal VRL and/or VRH are used for A/D reference (VCFG< ...
Page 109
... Bit is set ’0’ = Bit is cleared The A/D conversion results can be left justified (ADFM bit cleared), or right justified (ADFM bit set). Figure 11-1 through Figure 11-2 show the A/D result data format of the PIC16C717/770/771. ADRESH (1Eh) bit7 12-bit A/D Result MSB ...
Page 110
... PIC16C717/770/771 FIGURE 11-2: PIC16C717 10-BIT A/D RESULT FORMAT (ADFM = 0) MSB bit7 (ADFM = 1) bit7 Unused After the A/D module has been configured as desired, the selected channel must be acquired before the con- version is started. The analog input channels must have their corresponding TRIS and ANSEL bits selected as an input ...
Page 111
... A/D VCFG<2:0> C ONVERTER V - REF (R EFERENCE -) VOLTAGE VCFG<2:0> 2002 Microchip Technology Inc. PIC16C717/770/771 4. Wait the required acquisition time. 5. START conversion • Set GO/DONE bit (ADCON0) 6. Wait 13T until A/D conversion is complete either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 7 ...
Page 112
... PIC16C717/770/771 11.3 Selecting the A/D Conversion Clock The A/D conversion cycle requires 13T AD tling time, and 12 T for conversion. The source of the AD A/D conversion clock is software selected. If neither the internal VRH nor VRL are used for the A/D converter, the four possible options for T ...
Page 113
... Then the ; conversion may be started. BSF ADCON0, GO ;Start A/D Conversion : ;The ADIF bit will be ;set and the GO/DONE bit : ;cleared upon completion- ;of the A/D conversion. ; Wait for A/D completion and read ADRESH:ADRESL for result. 2002 Microchip Technology Inc. PIC16C717/770/771 DS41120B-page 111 ...
Page 114
... PIC16C717/770/771 11.5 A/D Converter Module Operation Figure 11-4 shows the flowchart of the A/D converter module. FIGURE 11-4: FLOW CHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Sample Selected Channel Yes Yes Start of A/D A/D Clock Conversion Delayed = RC? 1 Instruction Cycle No Yes Abort Conversion ...
Page 115
... This equation assumes that 1/4 LSb error is used (16384 steps for the A/D). The 1/4 LSb error is the maximum error allowed for the A/D to meet its specified resolution. The C is assumed for the 12-bit HOLD A/D. 2002 Microchip Technology Inc. PIC16C717/770/771 EXAMPLE 11- --------------- - – ...
Page 116
... PIC16C717/770/771 EXAMPLE 11-3: CALCULATING THE MINIMUM REQUIRED SAMPLE TIME T = Amplifier Settling Time ACQ + Holding Capacitor Charging Time +Temperature offset † ACQ + [(Temp - 25 C)(0.05 s/ C)] † Holding Capacitor Charging Time (1/16384) C HOLD - + 2 (1/16384 -25 pF (13 (1/16384 -0.338 (-9.704 3 ACQ + 3 [( C)( 1.25 s ...
Page 117
... The value that is in the ADRESH and ADRESL registers are not modified. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. 2002 Microchip Technology Inc. PIC16C717/770/771 11.9 Faster Conversion - Lower Resolution Trade-off Not all applications require a result with 12 bits of reso- lution, but may instead require a faster conversion time ...
Page 118
... PIC16C717/770/771 11.10 A/D Operation During SLEEP The A/D module can operate during SLEEP mode. This requires that the A/D clock source be configured for RC (ADCS<1:0> = 11b). With the RC clock source selected, when the GO/DONE bit is set the A/D module waits one instruction cycle before starting the conver- sion cycle ...
Page 119
... Additional information on special features is available in the PICmicro™ Mid-Range MCU Family Reference Manual, (DS33023). 2002 Microchip Technology Inc. PIC16C717/770/771 12.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in pro- gram memory location 2007h ...
Page 120
... PIC16C717/770/771 REGISTER 12-1: CONFIGURATION WORD FOR 16C717/770/771 DEVICE CP CP BORV1 BORV0 CP bit13 bit 13-12, CP: Program Memory Code Protection 9 Code protection off 0 = All program memory is protected bit 11-10: BORV<1:0>: Brown-out Reset Voltage bits set to 4.5V BOR set to 4.2V BOR set to 2.7V BOR set to 2 ...
Page 121
... Oscillator Configurations 12.2.1 OSCILLATOR TYPES The PIC16C717/770/771 can be operated in eight dif- ferent Oscillator modes. The user can program three configuration bits (FOSC<2:0>) to select one of these eight modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • ER External Resistor (with and without CLKOUT) • ...
Page 122
... RESET. DS41120B-page 120 12.2.6 CLKOUT In the INTRC and ER modes, the PIC16C717/770/771 can be configured to provide a clock out signal by pro- gramming the configuration word. The oscillator fre- quency, divided by 4, can be used for test purposes or to synchronize other logic. ...
Page 123
... RESET The PIC16C717/770/771 devices have several differ- ent RESETS. These RESETS are grouped into two classifications; power-up and non-power-up. The power-up type RESETS are the Power-on and Brown- out Resets which assume the device V normal operating range for the device’s configuration. ...
Page 124
... RESET CIRCUIT (FOR SLOW V RAMP MCLR PIC16C717/770/771 C Note 1: External Power-on Reset circuit is required only if V power-up slope is too DD slow. The diode D helps discharge the capacitor quickly when < recommended to make sure that voltage drop across R does not violate the device’s electrical specification. ...
Page 125
... Interrupt wake-up from SLEEP, GIE = 0 Interrupt wake-up from SLEEP, GIE = 1 Legend unchanged unknown unimplemented bit read as '0'. 2002 Microchip Technology Inc. PIC16C717/770/771 Table 12-5 shows the RESET conditions for some spe- cial function registers, while Table 12-6 shows the RESET conditions for all the registers. ...
Page 126
... PIC16C717/770/771 TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Power-on Reset or W INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 OPTION_REG TRISA TRISB PIE1 PIE2 PCON ...
Page 127
... See Table 12-5 for RESET value for specific condition. FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2002 Microchip Technology Inc. PIC16C717/770/771 MCLR Reset or Brown-out Reset WDT Reset 0000 0000 0000 0000 0000 ---- 0000 ---- --00 0101 --00 0101 --11 1111 ...
Page 128
... PIC16C717/770/771 FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-9: SLOW V RISE TIME (MCLR TIED TO V ...
Page 129
... TMR1IF TMR1IE BCLIF BCLIE 2002 Microchip Technology Inc. PIC16C717/770/771 The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the spe- cial function registers PIR1 and PIR2. The correspond- ...
Page 130
... PIC16C717/770/771 12.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt ...
Page 131
... Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for the full description of the configuration word bits. 2002 Microchip Technology Inc. PIC16C717/770/771 wake-up and continue with normal operation (Watch- dog Timer Wake-up). The TO bit in the STATUS regis- ter will be cleared upon a Watchdog Timer time-out ...
Page 132
... PIC16C717/770/771 12.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance) ...
Page 133
... These locations are not accessible during normal execution but are read- able and writable during program/verify recom- mended that only the 4 Least Significant bits of the ID location are used. 2002 Microchip Technology Inc. PIC16C717/770/771 (1) T OST Interrupt Latency Processor in ...
Page 134
... PIC16C717/770/771 NOTES: DS41120B-page 132 2002 Microchip Technology Inc. ...
Page 135
... If a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time 2002 Microchip Technology Inc. PIC16C717/770/771 Table 13-2 lists the instructions recognized by the MPASM™ assembler. Figure 13-1 shows the general formats that the instruc- tions can have ...
Page 136
... PIC16C717/770/771 TABLE 13-2: PIC16CXXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 137
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. 2002 Microchip Technology Inc. PIC16C717/770/771 ANDWF AND W with f Syntax: [label] ANDWF f,d Operands 127 d Operation: (W) .AND. (f) (destination) ...
Page 138
... PIC16C717/770/771 BTFSS Bit Test f, Skip if Set Syntax: [label] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ’b’ in register ’f’ is ’0’, the next instruction is executed. If bit ’b’ is ’1’, then the next instruc- ...
Page 139
... W register. If ’d’ the result is placed back in reg- ister ’f’. If the result is 1, the next instruc- tion is executed. If the result is 0, then a NOP is executed instead making instruction. CY 2002 Microchip Technology Inc. PIC16C717/770/771 GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands 2047 ...
Page 140
... PIC16C717/770/771 IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k Operands 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W reg- ister. IORWF Inclusive OR W with f Syntax: [ label ] IORWF Operands: ...
Page 141
... Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 2002 Microchip Technology Inc. PIC16C717/770/771 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 ...
Page 142
... PIC16C717/770/771 SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands 127 ...
Page 143
... Customizable toolbar and key mapping • A status bar • On-line help 2002 Microchip Technology Inc. PIC16C717/770/771 The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- matically updates all project information) • ...
Page 144
... PIC16C717/770/771 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for pre- compiled code to be used with the MPLINK object linker ...
Page 145
... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2002 Microchip Technology Inc. PIC16C717/770/771 14.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...
Page 146
... PIC16C717/770/771 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple dem- onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Mod- ule. All the necessary hardware and software is included to run the basic demonstration programs ...
Page 147
... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16C8X PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers 2002 Microchip Technology Inc. PIC16C717/770/771 Kits Eval and Boards Demo DS41120B-page 145 ...
Page 148
... PIC16C717/770/771 NOTES: DS41120B-page 146 2002 Microchip Technology Inc. ...
Page 149
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. PIC16C717/770/771 (except V , MCLR and RA4) .......................................... -0. ...
Page 150
... PIC16C717/770/771 FIGURE 15-1: PIC16C717/770/771 VOLTAGE-FREQUENCY GRAPH, -40 C 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. ...
Page 151
... FIGURE 15-3: PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH, - 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2002 Microchip Technology Inc. PIC16C717/770/771 Frequency (MHz DS41120B-page 149 ...
Page 152
... PIC16C717/770/771 15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended) PIC16LC717/770/771 (Commercial, Industrial, Extended) PIC16LC717/770/771 PIC16C717/770/771 Param. Sym Characteristic No. D001 V Supply Voltage DD D001 V Supply Voltage DD D002* V RAM Data Retention DR (1) Voltage D002* V RAM Data Retention DR (1) Voltage D003 start voltage to POR DD ensure internal Power- ...
Page 153
... DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended) PIC16LC717/770/771 (Commercial, Industrial, Extended) (Continued) PIC16LC717/770/771 PIC16C717/770/771 Param. Sym Characteristic No. I (2) DD Supply Current D010D PIC16LC7XX D010E D010G D010K I (2) DD Supply Current D010 PIC16C7XX D010A D010B D010C D010F D010H D010J * These parameters are characterized but not tested. ...
Page 154
... PIC16C717/770/771 PIC16LC717/770/771 PIC16C717/770/771 Param. Sym Characteristic No Power-down Current D020D PIC16LC7XX D020E D020F D020G D020 PIC16C7XX D020A D020B D020C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 155
... DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended) PIC16LC717/770/771 (Commercial, Industrial, Extended) (Continued) PIC16LC717/770/771 PIC16C717/770/771 Param. Sym Characteristic No. Base plus Module current D021A I Watchdog Timer WDT D021 I Watchdog Timer WDT D021 I Watchdog Timer WDT D025 I 1 Timer1 Oscillator T OSC D025 I 1 Timer1 Oscillator ...
Page 156
... PIC16C717/770/771 15.2 DC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param. Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR D033 OSC1 (in XT, HS, LP and EC) Input High Voltage V I/O ports IH with TTL buffer ...
Page 157
... AC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771 (Commercial, Industrial, Extended) 15.3.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port ...
Page 158
... PIC16C717/770/771 FIGURE 15-4: LOAD CONDITIONS Load condition Pin 464 for all pins except OSC2 for OSC2 output DS41120B-page 156 Load condition Pin 2002 Microchip Technology Inc. ...
Page 159
... Note 1: Measurements are taken ER or INTRC w/CLKOUT mode where CLKOUT output 2002 Microchip Technology Inc. PIC16C717/770/771 20, 21 Min — — — 0.25T + — PIC16C717/770/771 100 PIC16LC717/770/771 200 0 PIC16C717/770/771 — PIC16LC717/770/771 — PIC16C717/770/771 — PIC16LC717/770/771 — new value Typ† Max Unit Conditions s 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — ...
Page 160
... PIC16C717/770/771 FIGURE 15-6: EXTERNAL CLOCK TIMING Q4 OSC1 TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param No. Sym Characteristic 1A F External CLKIN Frequency OSC (Note 1) Oscillator Frequency (Note External CLKIN Period OSC (Note 1) Oscillator Period (Note Instruction Cycle Time (Note TosL, External Clock in (OSC1) High or Low ...
Page 161
... TABLE 15-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC16C717/770/771 AND PIC16LC717/770/771 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C Operating Voltage V Parameter Sym No. Internal Calibrated RC Frequency F IRC Internal RC Frequency* * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 162
... PIC16C717/770/771 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic No. 30* T MCLR Pulse Width (low) MCL 31* T Watchdog Timer Time-out Period WDT (No Prescaler) 32* T Oscillation Start-up Timer Period OST 33* T Power up Timer Period ...
Page 163
... T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width 42* Tt0P T0CKI Period 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Prescaler = 2,4,8 Asynchronous PIC16C717/770/771 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 Synchronous, Prescaler = 2,4,8 Asynchronous PIC16C717/770/771 47* Tt1P T1CKI input period Synchronous Asynchronous PIC16C717/770/771 ...
Page 164
... DS41120B-page 162 Min Typ† Max Units Conditions 0. — CY PIC16C717/770/771 10 — PIC16LC717/770/771 20 — 0. — CY PIC16C717/770/771 10 — PIC16LC717/770/771 20 — — PIC16C717/770/771 — 10 PIC16LC717/770/771 — 25 PIC16C717/770/771 — 10 PIC16LC717/770/771 — 25 — ns — ns — ns — ns — ns — ns — prescale value ( 16 2002 Microchip Technology Inc. ...
Page 165
... Analog Peripherals Characteristics: PIC16C717/770/771 & PIC16LC717/770/771 (Commercial, Industrial, Extended) 15.4.1 BANDGAP MODULE FIGURE 15-12: BANDGAP START-UP TIME V BGAP Enable Bandgap Bandgap stable TABLE 15-7: BANDGAP START-UP TIME Param. Sym Characteristic No. 36* T Bandgap start-up time BGAP * These parameters are characterized but not tested. ...
Page 166
... PIC16C717/770/771 15.4.2 LOW VOLTAGE DETECT MODULE (LVD) FIGURE 15-13: LOW VOLTAGE DETECT CHARACTERISTICS (LVDIF set by hardware) LVDIF TABLE 15-8: ELECTRICAL CHARACTERISTICS: LVD Standard Operating Conditions (unless otherwise stated) Operating temperature DC CHARACTERISTICS Operating voltage V Param. Characteristic No. D420* LVD Voltage LVV = 0100 LVV = 0101 ...
Page 167
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc. PIC16C717/770/771 0°C ≤ T ≤ +70°C for commercial A -40° ...
Page 168
... PIC16C717/770/771 15.4.5 A/D CONVERTER MODULE TABLE 15-11: PIC16C770/771 AND PIC16LC770/771 A/D CONVERTER CHARACTERISTICS: Param. Sym Characteristic No. A01 N Resolution R A03 E Integral error IL A04 E Differential error DL A06 E Offset error OFF A07 E Gain Error GN A10 — Monotonicity A20* V Reference voltage REF ( REF REF A21* ...
Page 169
... Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D RC clock source is selected, a time of T instruction to be executed. 2002 Microchip Technology Inc. PIC16C717/770/771 131 130 OLD_DATA SAMPLING STOPPED is added before the A/D clock starts. This allows the SLEEP CY ...
Page 170
... PIC16C717/770/771 TABLE 15-12: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENTS (NORMAL MODE) Parameter Sym Characteristic No. (3) T A/D clock period AD 130* 131* T Conversion time CNV (not including acquisition time) (Note 1) 132* T Acquisition Time ACQ 134 A/D clock GO start * These parameters are characterized but not tested. ...
Page 171
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 11.6 for minimum conditions. 3: These numbers multiplied 2002 Microchip Technology Inc. PIC16C717/770/771 131 130 ...
Page 172
... PIC16C717/770/771 TABLE 15-14: PIC16C717 AND PIC16LC717 A/D CONVERTER CHARACTERISTICS: Param. Sym Characteristic No. A01 N Resolution R A03 E Integral error IL A04 E Differential error DL A06 E Offset error OFF A07 E Gain Error GN A10 — Monotonicity A20* V Reference voltage REF ( REF REF A21* V Reference V High + REF ( VDD ...
Page 173
... Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D RC clock source is selected, a time of T instruction to be executed. TABLE 15-15: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (NORMAL MODE) Parameter Sym Characteristic No. (3) T A/D clock period AD 130* 131* T Conversion time (not ...
Page 174
... Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D RC clock source is selected, a time of T instruction to be executed. TABLE 15-16: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (SLEEP MODE) Parameter Sym Characteristic No. (3) T A/D clock period AD 130* 131* T Conversion time (not ...
Page 175
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 2002 Microchip Technology Inc. PIC16C717/770/771 MSb ...
Page 176
... PIC16C717/770/771 FIGURE 15-19: SPI MASTER MODE TIMING (CKE = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. TABLE 15-18: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. Symbol Characteristic No. 71* TscH SCK input high time ...
Page 177
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 2002 Microchip Technology Inc. PIC16C717/770/771 ...
Page 178
... PIC16C717/770/771 FIGURE 15-21: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. TABLE 15-20: SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. Symbol Characteristic No. 70* TssL2scH SCK or SCK input ...
Page 179
... Maximum pin capacitance = 10 pF for all I FIGURE 15-23: MASTER SSP I 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 15-4 for load conditions. 2002 Microchip Technology Inc. PIC16C717/770/771 2 C BUS START/STOP BITS TIMING WAVEFORMS Min Typ Max 2(T )(BRG + 1) — OSC 2(T )(BRG + 1) — OSC (1) ...
Page 180
... PIC16C717/770/771 2 TABLE 15-22: MASTER SSP I C BUS DATA REQUIREMENTS Param. Symbol Characteristic No. 100* T Clock high time HIGH 101* T Clock low time LOW 102* T SDA and SCL R rise time 103* T SDA and SCL F fall time 90 START condition SU STA setup time 91 START condition ...
Page 181
... V OSC DD FIGURE 16-1: MAXIMUM I DD 6.0 5.0 4.0 3.0 2.0 1.0 0.0 4.00 6.00 8.00 2002 Microchip Technology Inc. PIC16C717/770/771 VS. F OVER V (HS MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10.00 12.00 14.00 F ...
Page 182
... PIC16C717/770/771 FIGURE 16-2: TYPICAL I DD 6.0 5.0 4.0 3.0 2.0 1.0 0.0 4.00 6.00 8.00 FIGURE 16-3: MAXIMUM I DD 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.00 0.50 1.00 DS41120B-page 180 VS. F OVER V (HS MODE) OSC DD 5.5V 5.0V 4.5V 4 ...
Page 183
... FIGURE 16-5: MAXIMUM I DD 0.140 0.120 0.100 0.080 0.060 0.040 0.020 0.000 0.02 0.03 0.04 2002 Microchip Technology Inc. PIC16C717/770/771 VS. F OVER V (XT MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 1.50 2.00 2.50 F (MHz) OSC VS ...
Page 184
... PIC16C717/770/771 FIGURE 16-6: TYPICAL I DD 0.120 0.100 0.080 0.060 0.040 0.020 0.000 0.02 0.03 0.04 FIGURE 16-7: MAXIMUM I DD 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.00 2.00 4.00 6.00 DS41120B-page 182 VS. F OVER V (LP MODE) OSC DD 5 ...
Page 185
... FIGURE 16-9: MAXIMUM I DD 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 VS. F OVER V (EC MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 6.00 8.00 10.00 12.00 F (MHz) OSC VS ...
Page 186
... PIC16C717/770/771 FIGURE 16-10: TYPICAL I DD 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 FIGURE 16-11: TYPICAL F OSC 10.0 1.0 0.1 2.5 3.0 DS41120B-page 184 VS. F OVER V (ER MODE) OSC 38 38 100 100 200 200 499 499 3.5 4.0 4.5 ...
Page 187
... FIGURE 16-13: TYPICAL I DD 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 VS. V (INTRC 37 kHZ MODE) DD Typ (25 °C) 3.5 4.0 V (Volts) DD VS. V (INTRC 37 kHZ MODE) DD -40 °C 25 °C 85 °C 125 °C 3 ...
Page 188
... PIC16C717/770/771 FIGURE 16-14: INTERNAL RC F 0.060 0.055 0.050 0.045 0.040 0.035 0.030 0.025 0.020 2.5 3.0 FIGURE 16-15: MAXIMUM AND TYPICAL I 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.5 3.0 DS41120B-page 186 VS. V OVER TEMPERATURE (37 kHZ) OSC DD Max (125 °C) Typ (25 °C) Min(-40° ...
Page 189
... FIGURE 16-17: INTERNAL RC F 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 VS. V (INTRC 4 MHz MODE) DD 125 °C 85 °C 3.5 4.0 V (Volts) DD VS. V OVER TEMPERATURE (4 MHz) OSC DD Max (125 °C) Typ (25 °C) Min (-40 ° ...
Page 190
... PIC16C717/770/771 FIGURE 16-18: MAXIMUM 0.1 0.01 2.5 3.0 DS41120B-page 188 ° ° VS +125 C) DD +125°C +85°C +25°C 3.5 4.0 V (V) DD -40°C 4.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 191
... FIGURE 16-19: TYPICAL AND MAXIMUM I 16.0 14.0 12.0 10.0 P 8.0 ' 6.0 4.0 2.0 0.0 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° VS +125 WDT DD Max (-40°C) 3.5 4.0 4.5 V (V) DD ° C) Typ (25°C) 5.0 5.5 DS41120B-page 189 ...
Page 192
... PIC16C717/770/771 FIGURE 16-20: TYPICAL AND MAXIMUM I 150.0 130.0 110.0 90 70.0 50.0 30.0 10.0 2.5 3.0 FIGURE 16-21: TYPICAL AND MAXIMUM I 350.0 330.0 310.0 290.0 270.0 P 250.0 ' 230.0 210.0 190.0 170.0 150.0 2.5 3.0 DS41120B-page 190 VS. V (32 KHZ, -40 TMR1 DD Max (-40°C) 3.5 4 ...
Page 193
... FIGURE 16-23: TYPICAL AND MAXIMUM I 75.0 70.0 65.0 60.0 55 50.0 45.0 40.0 35.0 30.0 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° VS +125 VRH DD Max (125°C) Max (85°C) Typ (25°C) 5.0 V (V) DD ° VS +125 LVD DD Max (125° ...
Page 194
... PIC16C717/770/771 FIGURE 16-24: TYPICAL AND MAXIMUM I 75.0 70.0 65.0 60.0 55 50.0 45.0 40.0 35.0 30.0 2.5 3.0 FIGURE 16-25: TYPICAL AND MAXIMUM I 90.0 Max (125°C) 80.0 70.0 Typ (25°C) P 60.0 ' 50.0 40.0 RESET Device in Reset Indeterminate 30.0 2.0 2.5 DS41120B-page 192 ° ...
Page 195
... FIGURE 16-27: V VS 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 5.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° VS +125 BOR DD Max (125 °C) Typ (25 °C) Device in Reset RESET 3.5 4.0 4.5 V (V) DD ° ° +125 ...
Page 196
... PIC16C717/770/771 FIGURE 16-28: V VS 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 5.0 FIGURE 16-29: V VS 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -2.0 -4.0 DS41120B-page 194 ° ° +125 5.0V) DD Max (125°C) Typ (25°C) Min (-40°C) 10 ...
Page 197
... FIGURE 16-31: MINIMUM AND MAXIMUM V 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.5 3.0 2002 Microchip Technology Inc. PIC16C717/770/771 ° ° +125 5.0V) DD Max (-40°C) Typ (25°C) Min (125°C) -10.0 -15.0 I (mA VS. V (TTL INPUT,-40 ...
Page 198
... PIC16C717/770/771 FIGURE 16-32: MINIMUM AND MAXIMUM V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 FIGURE 16-33: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD VS. V 35.0 30.0 25.0 20.0 15.0 10.0 2.5 3.0 DS41120B-page 196 /V VS. V (ST INPUT,- Max High (125°C) Min High (-40° ...
Page 199
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. PIC16C717/770/771 Example PIC16C717/P 9917017 Example PIC16C717/JW 9905017 Example PIC16C717/SO 9910017 Example PIC16C770/P 9917017 DS41120B-page 197 ...
Page 200
... PIC16C717/770/771 17.1 Package Marking Information (Cont’d) 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 20-Lead CERDIP Windowed XXXXXXXX XXXXXXXX YYWWNNN 20-Lead SOIC XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXX YYWWNNN DS41120B-page 198 Example PIC16C770 20I/SS 9917017 Example PIC16C770/JW 9905017 Example PIC16C771/SO 9910017 2002 Microchip Technology Inc. ...