PIC16C717-I/SO Microchip Technology, PIC16C717-I/SO Datasheet - Page 94

• Manufacturer Part Number: PIC16C717-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C717-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6 bit
• Data Rom Size: 256 B
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C717I/SO

PIC16C717/770/771
9.2.15
The master asserts a STOP condition on the SDA and
SCL pins at the end of a receive/transmit by setting the
Stop Sequence Enable bit PEN (SSPCON2<2>). At the
end of a receive/transmit plus Acknowledge, the SCL
line is held low immediately following the falling edge of
the ninth SCL pulse. When the PEN bit is set, the mas-
ter will assert the SDA line low. When the SDA line is
sampled low, the baud rate generator is loaded from
SSPADD<6:0> and counts down to 0. When the baud
rate generator times out, the SCL pin is brought high,
the BRG is reloaded and one T
tor rollover count) later, the SDA pin is de-asserted.
The SDA pin transition from low to high while SCL is
high is the STOP condition and causes the P bit (SSP-
STAT<4>) to be set. Following this the baud rage gen-
erator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the baud rate generator
FIGURE 9-21:
DS41120B-page 92
STOP CONDITION TIMING
SCL
SDA
Note: T
Write to SSPCON2
Falling edge of
9th clock
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
NACK
= one baud rate generator period.
Set PEN
BRG
(baud rate genera-
SDA asserted low before rising edge of clock
to setup STOP condition.
T
T
BRG
BRG
Advance Information
T
SCL brought high after T
BRG
P bit (SSPSTAT<4>) is set
P
T
BRG
times out (T
the PEN bit is cleared and the SSPIF bit is set
(Figure 9-21).
Whenever the firmware decides to take control of the
bus, it should first determine if the bus is busy by check-
ing the S and P bits in the SSPSTAT register. When the
MSSP module detects a START or STOP condition the
SSPIF flag is set. If the bus is busy (S bit is set), then
the CPU can be configured to be interrupted when
when the bus is free by enabling the SSPIF interrupt to
detect the STOP bit.
9.2.15.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
BRG
WCOL STATUS FLAG
BRG
) the STOP condition is complete and
2002 Microchip Technology Inc.