PIC16F627-20E/SO Microchip Technology, PIC16F627-20E/SO Datasheet - Page 86

• Manufacturer Part Number: PIC16F627-20E/SO
• Description: IC MCU FLASH 1KX14 18-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627-20E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

PIC16F62X
FIGURE 12-14:
12.5
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
12.5.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
DS40300C-page 84
RB1/RX/DT PIN
RB2/TX/CK PIN
RCIF BIT
(INTERRUPT)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).
Note 1: Timing diagram demonstrates Sync Master mode with bit SREN = ‘1’ and bit BRG = ‘0’.
WRITE TO
BIT SREN
CREN BIT
SREN BIT
USART Synchronous Slave Mode
READ
RXREG
USART SYNCHRONOUS SLAVE
TRANSMIT
Q2
'0'
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
BIT0
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BIT1
Preliminary
BIT2
BIT3
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
BIT4
BIT5
BIT6
 2003 Microchip Technology Inc.
BIT7
Q1 Q2 Q3 Q4
'0'