ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 181

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.5
4.15.5.1
4.15.5.2
9132D–AUTO–12/10
Register Descriptions
USIDR – USI Data Register
USIBR – USI Buffer Register
• Bits 7:0 – USID7..0: USI Data
When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly.
If a serial clock occurs at the same cycle the register is written, the register will contain the
value written and no shift is performed. A (left) shift operation is performed depending of the
USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a
Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note
that even when no wire mode is selected (USIWM1..0 = 0) both the external data input
(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output
latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transpar-
ent) during the first half of a serial clock cycle when an external clock source is selected
(USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The
output will be changed immediately when a new MSB written as long as the latch is open. The
latch ensures that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register to the pin must be set to one for enabling
data output from the USI Data Register.
• Bits 7:0 – USID7..0: USI Buffer
The content of the Serial Register is loaded to the USI Buffer Register when the transfer is
completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data
Buffer can be accessed when the CPU reads the received data. This gives the CPU time to
handle other program tasks too as the controlling of the USI is not so timing critical. The USI
flags as set same as when reading the USIDR register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
USID7
USIB7
R/W
R
7
0
7
0
USID6
USIB6
R/W
R
6
0
6
0
USID5
USIB5
R/W
R
5
0
5
0
USID4
USIB4
R/W
R
4
0
4
0
Atmel ATA6616/ATA6617
USID3
USIB3
R/W
R
3
0
3
0
USID2
USIB2
R/W
R
2
0
2
0
USID1
USIB1
R/W
R
1
0
1
0
USID0
USIB0
R/W
R
0
0
0
0
USIDR
USIBR
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