ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 233
ATA6617-P3QW
Manufacturer Part Number
ATA6617-P3QW
Description
MCU W/LIN TX/5V REG/WTCDG 38VQFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6617-P3QW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6617-P3QW
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATA6617-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.18.12.4
9132D–AUTO–12/10
ADCSRB – ADC Control and Status Register B
• Bit 7– BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be
selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided
conversions are supported and the voltage on the positive input must always be larger than
the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In
the bipolar mode two-sided conversions are supported and the result is represented in the
two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the
resolution is 9 bits + 1 sign bit.
• Bit 3 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to
zero when ADCSRB register is written.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA register is written to one, the value of these bits selects which source
will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect.
A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that
switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA register is set, this will start a conver-
sion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the
ADC Interrupt Flag is set
Table 4-61.
Bit
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
ADC Auto Trigger Source Selections
R/W
BIN
7
0
ADTS1
0
0
1
1
0
0
1
1
ACME
.
R/W
6
0
ACIR1
R/W
5
0
ADTS0
0
1
0
1
0
1
0
1
ACIR0
R/W
4
0
Atmel ATA6616/ATA6617
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter1 Compare Match A
Timer/Counter1 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Capture Event
Watchdog Interrupt Request
R
3
–
0
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ADTS0 ADCSRB
R/W
0
0
233
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