PIC18LF13K22-I/ML Microchip Technology, PIC18LF13K22-I/ML Datasheet - Page 372

• Manufacturer Part Number: PIC18LF13K22-I/ML
• Description: IC PIC MCU FLASH 256KX8 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
I
ID Locations .............................................................. 255, 270
INCF.................................................................................. 292
INCFSZ ............................................................................. 293
In-Circuit Debugger ........................................................... 270
In-Circuit Serial Programming (ICSP) ....................... 255, 270
Indexed Literal Offset Addressing
Indexed Literal Offset Mode .............................................. 318
Indirect Addressing ............................................................. 44
INFSNZ ............................................................................. 293
Initialization Conditions for all Registers ........................... 251
Instruction Cycle.................................................................. 31
Instruction Flow/Pipelining .................................................. 31
Instruction Set ................................................................... 271
DS41365C-page 372
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C Mode (MSSP)
Acknowledge Sequence Timing................................ 168
Baud Rate Generator ................................................ 161
Bus Collision
Clock Arbitration........................................................ 162
Clock Stretching ........................................................ 154
Clock Synchronization and the CKP bit (SEN = 1) ... 155
Effects of a Reset...................................................... 169
General Call Address Support .................................. 158
I
Master Mode ............................................................. 159
Multi-Master Communication, Bus Collision and
Multi-Master Mode .................................................... 169
Operation .................................................................. 146
Read/Write Bit Information (R/W Bit) ................ 146, 147
Registers ................................................................... 142
Serial Clock (RC3/SCK/SCL) .................................... 147
Slave Mode ............................................................... 146
Sleep Operation ........................................................ 169
Stop Condition Timing............................................... 168
and Standard PIC18 Instructions .............................. 318
Clocking Scheme ........................................................ 31
ADDLW ..................................................................... 277
ADDWF ..................................................................... 277
ADDWF (Indexed Literal Offset Mode) ..................... 319
ADDWFC .................................................................. 278
ANDLW ..................................................................... 278
ANDWF ..................................................................... 279
BC ............................................................................. 279
BCF ........................................................................... 280
BN ............................................................................. 280
BNC .......................................................................... 281
BNN .......................................................................... 281
BNOV ........................................................................ 282
BNZ ........................................................................... 282
BOV .......................................................................... 285
BRA........................................................................... 283
2
C Clock Rate w/BRG .............................................. 161
During a Repeated Start Condition ................... 172
During a Stop Condition.................................... 173
10-Bit Slave Receive Mode (SEN = 1).............. 154
10-Bit Slave Transmit Mode.............................. 154
7-Bit Slave Receive Mode (SEN = 1)................ 154
7-Bit Slave Transmit Mode................................ 154
Operation .......................................................... 160
Reception.......................................................... 165
Repeated Start Condition Timing...................... 164
Start Condition Timing ...................................... 163
Transmission..................................................... 165
Arbitration.......................................................... 169
Addressing ........................................................ 146
Reception.......................................................... 147
Transmission..................................................... 147
Preliminary
INTCON Register................................................................ 67
INTCON Registers........................................................ 67–69
INTCON2 Register.............................................................. 68
INTCON3 Register.............................................................. 69
Inter-Integrated Circuit. See I
BSF........................................................................... 283
BSF (Indexed Literal Offset Mode) ........................... 319
BTFSC ...................................................................... 284
BTFSS ...................................................................... 284
BTG .......................................................................... 285
BZ ............................................................................. 286
CALL......................................................................... 286
CLRF ........................................................................ 287
CLRWDT .................................................................. 287
COMF ....................................................................... 288
CPFSEQ ................................................................... 288
CPFSGT ................................................................... 289
CPFSLT .................................................................... 289
DAW ......................................................................... 290
DCFSNZ ................................................................... 291
DECF ........................................................................ 290
DECFSZ ................................................................... 291
Extended Instruction Set .......................................... 313
General Format......................................................... 273
GOTO ....................................................................... 292
INCF ......................................................................... 292
INCFSZ..................................................................... 293
INFSNZ..................................................................... 293
IORLW ...................................................................... 294
IORWF...................................................................... 294
LFSR ........................................................................ 295
MOVF ....................................................................... 295
MOVFF ..................................................................... 296
MOVLB ..................................................................... 296
MOVLW .................................................................... 297
MOVWF .................................................................... 297
MULLW..................................................................... 298
MULWF..................................................................... 298
NEGF........................................................................ 299
NOP .......................................................................... 299
Opcode Field Descriptions........................................ 272
POP .......................................................................... 300
PUSH........................................................................ 300
RCALL ...................................................................... 301
RESET...................................................................... 301
RETFIE ..................................................................... 302
RETLW ..................................................................... 302
RETURN................................................................... 303
RLCF ........................................................................ 303
RLNCF...................................................................... 304
RRCF........................................................................ 304
RRNCF ..................................................................... 305
SETF ........................................................................ 305
SETF (Indexed Literal Offset Mode) ......................... 319
SLEEP ...................................................................... 306
SUBFWB .................................................................. 306
SUBLW ..................................................................... 307
SUBWF..................................................................... 307
SUBWFB .................................................................. 308
SWAPF ..................................................................... 308
TBLRD ...................................................................... 309
TBLWT ..................................................................... 310
TSTFSZ .................................................................... 311
XORLW .................................................................... 311
XORWF .................................................................... 312
© 2009 Microchip Technology Inc.
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