PIC18LF13K22-I/ML Microchip Technology, PIC18LF13K22-I/ML Datasheet - Page 53

IC PIC MCU FLASH 256KX8 20-QFN

PIC18LF13K22-I/ML

Manufacturer Part Number
PIC18LF13K22-I/ML
Description
IC PIC MCU FLASH 256KX8 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-I/ML

Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF13K22-I/ML
Manufacturer:
CAVIUM
Quantity:
155
FIGURE 4-3:
4.3
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 4-4:
© 2009 Microchip Technology Inc.
Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.
21
Reading the Flash Program
Memory
Instruction Register
(IR)
TBLPTRU
TABLE POINTER BOUNDARIES BASED ON OPERATION
READS FROM FLASH PROGRAM MEMORY
16
(Even Byte Address)
FETCH
15
TABLE ERASE/WRITE
TBLPTR<21:n+1>
TABLE READ – TBLPTR<21:0>
Program Memory
TBLPTRH
Preliminary
(1)
PIC18F1XK22/LF1XK22
(Odd Byte Address)
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 4-4
shows the interface between the internal program
memory and the TABLAT.
TBLPTR = xxxxx1
8
TBLRD
7
TBLPTRL
Read Register
TBLPTR<n:0>
TABLE WRITE
TABLAT
TBLPTR = xxxxx0
DS41365C-page 53
(1)
0

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