PIC18LF13K22-I/ML Microchip Technology, PIC18LF13K22-I/ML Datasheet - Page 376

• Manufacturer Part Number: PIC18LF13K22-I/ML
• Description: IC PIC MCU FLASH 256KX8 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
Timer3 ............................................................................... 109
Timing Diagrams
DS41365C-page 376
Operation .................................................................. 107
Output ....................................................................... 108
16-Bit Read/Write Mode............................................ 112
Associated Registers ................................................ 112
Operation .................................................................. 110
Oscillator ........................................................... 109, 112
Overflow Interrupt ............................................. 109, 112
Special Event Trigger (CCP)..................................... 112
TMR3H Register ....................................................... 109
TMR3L Register ........................................................ 109
A/D Conversion ......................................................... 351
Acknowledge Sequence ........................................... 168
Asynchronous Reception .......................................... 182
Asynchronous Transmission ..................................... 178
Asynchronous Transmission (Back to Back) ............ 179
Auto Wake-up Bit (WUE) During Normal Operation . 193
Auto Wake-up Bit (WUE) During Sleep .................... 193
Automatic Baud Rate Calculator ............................... 191
Baud Rate Generator with Clock Arbitration ............. 162
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ............................................ 347
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 171
Bus Collision During a Stop Condition (Case 1) ....... 173
Bus Collision During a Stop Condition (Case 2) ....... 173
Bus Collision During Start Condition (SDA only) ...... 170
Bus Collision for Transmit and Acknowledge............ 169
CLKOUT and I/O....................................................... 346
Clock Synchronization .............................................. 155
Clock Timing ............................................................. 343
Clock/Instruction Cycle ............................................... 31
Comparator Output ................................................... 217
Enhanced Capture/Compare/PWM (ECCP) ............. 350
Fail-Safe Clock Monitor (FSCM) ................................. 26
First Start Bit Timing ................................................. 163
Full-Bridge PWM Output ........................................... 122
Half-Bridge PWM Output .................................. 120, 127
I
I
I
I
I
I
I
I
I
I
I
I
Internal Oscillator Switch Timing................................. 23
PWM Auto-shutdown
PWM Direction Change ............................................ 123
PWM Direction Change at Near 100% Duty Cycle ... 124
PWM Output (Active-High)........................................ 118
PWM Output (Active-Low) ........................................ 119
Repeat Start Condition.............................................. 164
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................. 357
C Bus Start/Stop Bits.............................................. 356
C Master Mode (7 or 10-Bit Transmission) ............ 166
C Master Mode (7-Bit Reception) ........................... 167
C Slave Mode (10-Bit Reception, SEN = 0) ........... 150
C Slave Mode (10-Bit Reception, SEN = 1) ........... 157
C Slave Mode (10-Bit Transmission)...................... 151
C Slave Mode (7-bit Reception, SEN = 0).............. 148
C Slave Mode (7-Bit Reception, SEN = 1) ............. 156
C Slave Mode (7-Bit Transmission)........................ 149
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ......... 168
Condition........................................................... 171
(Case 1) ............................................................ 172
(Case 2) ............................................................ 172
(7 or 10-Bit Address Mode)............................... 158
Auto-restart Enabled ......................................... 126
Firmware Restart .............................................. 126
Preliminary
Timing Diagrams and Specifications
Timing Parameter Symbology .......................................... 342
Timing Requirements
Top-of-Stack Access........................................................... 28
TRISA Register................................................................... 81
TRISB Register............................................................. 86, 90
TSTFSZ ............................................................................ 311
Two-Speed Start-up.......................................................... 255
Two-Word Instructions
TXREG ............................................................................. 177
TXSTA Register................................................................ 184
U
USART
V
Voltage Reference (VR)
Voltage Reference. See Comparator Voltage
Voltage References
VRECON0 (Voltage Reference Control 0) Register ......... 241
VRECON1 (Voltage Reference Control 1) Register ......... 241
VRECON2 (Voltage Reference Control 2) Register ......... 242
Reset, WDT, OST and Power-up Timer ................... 347
Send Break Character Sequence ............................. 194
Slave Synchronization .............................................. 139
Slow Rise Time (MCLR Tied to V
SPI Master Mode (CKE = 1, SMP = 1) ..................... 354
SPI Mode (Master Mode).......................................... 138
SPI Mode (Slave Mode, CKE = 0) ............................ 140
SPI Mode (Slave Mode, CKE = 1) ............................ 140
SPI Slave Mode (CKE = 0) ....................................... 355
SPI Slave Mode (CKE = 1) ....................................... 355
Synchronous Reception (Master Mode, SREN) ....... 199
Synchronous Transmission ...................................... 196
Synchronous Transmission (Through TXEN) ........... 196
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock ........................... 349
Transition for Entry to Sleep Mode ........................... 231
Transition for Wake from Sleep (HSPLL) ................. 231
Transition Timing for Entry to Idle Mode................... 232
Transition Timing for Wake from Idle to Run Mode .. 232
USART Synchronous Receive (Master/Slave) ......... 353
USART Synchronous Transmission (Master/Slave). 353
A/D Conversion Requirements ................................. 351
PLL Clock ................................................................. 345
I
SPI Mode .................................................................. 356
Example Cases........................................................... 32
BRGH Bit .................................................................. 187
Synchronous Master Mode
Specifications ........................................................... 352
Reference (CV
Fixed Voltage Reference (FVR)................................ 239
VR Stabilization ........................................................ 239
2
C Bus Data..................................................... 358, 357
V
(MCLR Tied to V
Not Tied to V
Not Tied to V
Tied to V
Requirements, Synchronous Receive .............. 353
Requirements, Synchronous Transmission...... 353
Timing Diagram, Synchronous Receive ........... 353
Timing Diagram, Synchronous Transmission... 353
DD
Rise > T
DD
REF
, V
PWRT
DD
DD
)
DD
, Case 1) .................................. 248
, Case 2) .................................. 248
© 2009 Microchip Technology Inc.
DD
Rise < T
) ........................................... 249
) ......................................... 249
PWRT
DD
,
) ...................... 248