ATMEGA16A-MUR Atmel, ATMEGA16A-MUR Datasheet - Page 237
ATMEGA16A-MUR
Manufacturer Part Number
ATMEGA16A-MUR
Description
MCU AVR 16KB FLASH 16MHZ 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16A-MU.pdf
(352 pages)
Specifications of ATMEGA16A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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24.5.2
8154B–AVR–07/09
Boundary-scan and the Two-wire Interface
Figure 24-4. General Port Pin Schematic Diagram
Note:
The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – TWIEN. As shown in
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in
Notes:
1. See Boundary-scan description for details.
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to
Pxn
support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in
the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
drive contention.
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
Figure 24-9
IDxn
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
PUExn
is attached to the TWIEN signal.
SLEEP
OCxn
(1)
SYNCHRONIZER
ODxn
WDx:
RDx:
WPx:
RRx:
RPx:
CLK
D
L
Q
Q
I/O
Figure
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
Q
Q
24-5, the TWIEN signal enables
RESET
RESET
Q
Q
Q
Q
PORTxn
DDxn
CLR
CLR
D
D
ATmega16A
CLK
PUD
WDx
RDx
WPx
RRx
RPx
I/O
237
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