ATMEGA16A-MUR Atmel, ATMEGA16A-MUR Datasheet - Page 282

• Manufacturer Part Number: ATMEGA16A-MUR
• Description: MCU AVR 16KB FLASH 16MHZ 44QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.10.2
26.10.3
26.10.4
26.10.5
26.10.6
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ATmega16A
AVR_RESET ($C)
PROG_ENABLE ($4)
PROG_COMMANDS ($5)
PROG_PAGELOAD ($6)
PROG_PAGEREAD ($7)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking
the device out from the Reset Mode. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the Reset will be active as long as
there is a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-
bit Programming Enable Register is selected as Data Register. The active states are the
following:
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as Data Register. The active
states are the following:
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
The 1024 bit Virtual Flash Page Load Register is selected as Data Register. This is a virtual
scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register
is 8-bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the
Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the
Shift-DR state by an internal state machine. This is the only active state:
Note:
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port.
The 1032 bit Virtual Flash Page Read Register is selected as Data Register. This is a virtual
scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift
Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer
data to the Shift Register. The data are automatically transferred from the Flash page buffer byte
by byte in the Shift-DR state by an internal state machine. This is the only active state:
• Shift-DR: The Reset Register is shifted by the TCK input.
• Shift-DR: The programming enable signature is shifted into the Data Register.
• Update-DR: The programming enable signature is compared to the correct value, and
• Capture-DR: The result of the previous command is loaded into the Data Register.
• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous
• Update-DR: The programming command is applied to the Flash inputs
• Run-Test/Idle: One clock cycle is generated, executing the applied command (not always
• Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded
Programming mode is entered if the signature is valid.
command and shifting in the new command.
required, see
into the Flash page one byte at a time.
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
Table 26-14
below).
8154B–AVR–07/09