DSPIC30F2012-20I/ML Microchip Technology, DSPIC30F2012-20I/ML Datasheet - Page 135

• Manufacturer Part Number: DSPIC30F2012-20I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2012-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201220IML

TABLE 18-1:
© 2005 Microchip Technology Inc.
Wb
Wd
Wdo
Wm,Wn
Wm*Wm
Wm*Wn
Wn
Wnd
Wns
WREG
Ws
Wso
Wx
Wxd
Wy
Wyd
Field
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Base W register
Destination W register
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Dividend, Divisor working register pair (direct addressing)
Multiplicand and Multiplier working register pair for Square instructions
{W4*W4,W5*W5,W6*W6,W7*W7}
Multiplicand and Multiplier working register pair for DSP instructions
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
One of 16 working registers
One of 16 destination working registers
One of 16 source working registers
W0 (working register used in file register instructions)
Source W register
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
X data space pre-fetch address register for DSP instructions
X data space pre-fetch destination register for DSP instructions
Y data space pre-fetch address register for DSP instructions
Y data space pre-fetch destination register for DSP instructions
{[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
{[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
dsPIC30F2011/2012/3012/3013
{W0..W15}
{ Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Preliminary
{ Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
{W0..W15}
{W0..W15}
Description
{W0..W15}
{W4..W7}
{W4..W7}
DS70139C-page 133