PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 103

IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part Number
PIC24F16KA102-I/SS
Description
IC PIC MCU FLASH 16K 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SS

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
10.0
The PIC24F16KA102 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
• Clock frequency
• Instruction-based Sleep, Idle and Deep Sleep
• Software controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC bits. The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 8.0
“Oscillator Configuration”.
10.2
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. Deep Sleep mode stops clock
operation, code execution and all peripherals except
RTCC and DSWDT. It also freezes I/O states and
removes power to SRAM and Flash memory.
EXAMPLE 10-1:
© 2009 Microchip Technology Inc.
PWRSAV
PWRSAV
BSET
PWRSAV
Note:
modes
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
Instruction-Based Power-Saving
Modes
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
”Section 39. Power-Saving Features
with Deep Sleep” (DS39727).
#SLEEP_MODE
#IDLE_MODE
DSCON, #DSEN
#SLEEP_MODE
Family
PWRSAV
Reference
; Put the device into SLEEP mode
; Put the device into IDLE mode
; Enable Deep Sleep
; Put the device into Deep SLEEP mode
INSTRUCTION SYNTAX
Manual”,
Preliminary
PIC24F16KA102 FAMILY
The assembly syntax of the PWRSAV instruction is
shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
10.2.1
Sleep mode includes these features:
• The system clock source is shut down. If an
• The device current consumption will be reduced
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock will continue to run in Sleep
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
to a minimum provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
mode if the WDT or RTCC with LPRC as clock
source is enabled.
prior to entering Sleep mode.
continue to operate in Sleep mode. This includes
items, such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
enabled
Note:
SLEEP MODE
SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
DS39927B-page 101

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