ATTINY461-20SU Atmel, ATTINY461-20SU Datasheet - Page 177

• Manufacturer Part Number: ATTINY461-20SU
• Description: IC MCU AVR 4K FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY461-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 20SOIC
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 18-2. Serial Programming Instruction example
18.7
18.7.1
2588E–AVR–08/10
Byte 1
Parallel Programming
Signal Names
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Bit 15 B
Byte 2
Adr MSB
Adr dr M
A
r MS S B
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see
177.
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits. Pulses are assumed to be at least 250 ns in
length, unless otherwise noted.
In this section, some pins are referenced by signal names describing their functionality during
parallel programming, see
are referenced by pin names.
Byte 3
Adr LSB
Page Offset
0
Serial Programming Instruction
Byte 4
Program Memory/
EEPROM Memory
Figure 18-3
Page Buffer
Page N-1
Page 0
Page 1
Page 2
and
Byte 1
Table
Page Number
18-12. Pins not described in the following table
Bit 15 B
Byte 2
Write Program Memory Page/
Write EEPROM Memory Page
Adr MSB
Byte 3
Adr LSB
A A dr dr LS
LSB
SB
Figure 18-2 on page
0
Byte 4
177