ATTINY861V-10SU Atmel, ATTINY861V-10SU Datasheet - Page 47
![IC MCU AVR 8K FLASH 10MHZ 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY861V-10SU
Manufacturer Part Number
ATTINY861V-10SU
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
20SOIC
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861V-10SU
Manufacturer:
Atmel
Quantity:
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Part Number:
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- Download datasheet (5Mb)
8.4
8.4.1
8.4.2
2588E–AVR–08/10
Register Description
MCUSR – MCU Status Register
WDTCR – Watchdog Timer Control Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the
Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed
instead of a reset if a timeout in the Watchdog Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful
for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,
Bit
0x34 (0x54)
Read/Write
Initial Value
Bit
0x21 (0x41)
Read/Write
Initial Value
7
WDIF
R/W
0
7
–
R
0
6
WDIE
R/W
0
6
–
R
0
5
WDP3
R/W
0
5
–
R
0
4
WDCE
R/W
0
4
–
R
0
3
WDE
R/W
X
3
WDRF
R/W
See Bit Description
2
WDP2
R/W
0
2
BORF
R/W
1
WDP1
R/W
0
1
EXTRF
R/W
0
WDP0
R/W
0
0
PORF
R/W
WDTCR
MCUSR
47
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