ATTINY861V-10SU Atmel, ATTINY861V-10SU Datasheet - Page 73
![IC MCU AVR 8K FLASH 10MHZ 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY861V-10SU
Manufacturer Part Number
ATTINY861V-10SU
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
20SOIC
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861V-10SU
Manufacturer:
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Quantity:
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Part Number:
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11.3.1.1
11.3.2
2588E–AVR–08/10
External Clock Source
Prescaler Reset
Figure 11-2. Prescaler for Timer/Counter0
Note:
The prescaled clock has a frequency of f
Table 11-4 on page 85
The prescaler is free running, i.e. it operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count
occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,
256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to
program execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the T0 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects. See
PSR0
clk
T0
I/O
1. The synchronization logic on the input pins (
Synchronization
for details.
Table 11-4 on page 85
Clear
T
0
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
CLK_I/O
/8, f
for details.
T0)
CLK_I/O
is shown in
/64, f
clk
I/O
CLK_I/O
). The latch is transparent in the
Figure
Figure 11-3
/256, or f
11-3.
clk
T0
shows a functional
CLK_I/O
/1024. See
T0
). The
73
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