PIC18LF25K22-I/SP Microchip Technology, PIC18LF25K22-I/SP Datasheet - Page 49

• Manufacturer Part Number: PIC18LF25K22-I/SP
• Description: MCU 8BIT 32KB FLASH 3.6V 28SDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF25K22-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 7
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the pri-
mary clock occurs (see
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 3-1:
FIGURE 3-2:
TABLE 3-2:
 2010 Microchip Technology Inc.
010 or 001
010 or 001
IRCF<2:0>
Peripheral
Note 1: Clock transition typically occurs within 2-4 T
000
000
000
Program
Counter
SOSCI
OSC1
Note1: T
Clock
Clock
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
Output
2: Clock transition typically occurs within 2-4 T
SOSC
OSC1
Clock
INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
Q1
OST
SCS<1:0> bits Changed
Q2
= 1024 T
PC
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Figure
Q3
INTSRC
Q4
OSC
0
1
1
x
x
; T
Q1
3-3). When the clock
PLL
Q1
1
= 2 ms (approx). These intervals are not shown to scale.
T
OST
PC
(1)
2
Q2
Clock Transition
MFIOSEL
3
OSC
T
OSTS bit Set
Q3
PLL
Preliminary
.
x
0
1
0
1
OSC
(1)
.
(1)
PC + 2
n-1
Q4
MFIOFS = 0, HFIOFS = 0 LFINTOSC
MFIOFS = 0, HFIOFS = 1 HFINTOSC
MFIOFS = 1, HFIOFS = 0 MFINTOSC
MFIOFS = 0, HFIOFS = 1 HFINTOSC
MFIOFS = 1, HFIOFS = 0 MFINTOSC
n
Q1
1
Transition
PIC18(L)F2X/4XK22
2
Clock
n-1 n
(2)
Q2
INTOSC Stability Indication
PC + 2
Q3
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
DS41412D-page 49
Q3
Q3