PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 15

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.1.2
It is possible to erase a single row (1024 bytes of data),
provided the block is not code-protected. Rows are
located at static boundaries, beginning at program
memory address, 000000h, extending to the internal
program memory limit (see Section 2.2 “Memory
Maps”).
The Row Erase duration is internally timed. After the
WR bit in EECON1 is set, a NOP is issued, where the
4th PGC is held high for the duration of the Row Erase
time, P10.
The
PIC18F6XJXX/8XJXX device is shown in Table 3-2. The
flowchart, shown in Figure 3-3, depicts the logic neces-
sary to completely erase a PIC18F6XJXX/8XJXX
device. The timing diagram that details the “Row Erase”
operation and parameter, P10, is shown in Figure 3-3.
TABLE 3-2:
 2009 Microchip Technology Inc.
Step 1: Enable memory writes.
Step 2: Point to first row in code memory.
Step 3: Enable erase and erase single row.
Step 4: Repeat step 3, with Address Pointer incremented by 1024 until all rows are erased.
Note:
Command
0000
0000
0000
0000
0000
0000
0000
4-Bit
code
ICSP ROW ERASE
The TBLPTR register can point at any byte
within the row intended for erase.
sequence
84 A6
6A F8
6A F7
6A F6
88 A6
82 A6
00 00
ERASE CODE MEMORY CODE SEQUENCE
Data Payload
to
Row
BSF
CLRF
CLRF
CLRF
BSF
BSF
NOP – hold PGC high for time P10.
Erase
EECON1, WREN
TBLPTRU
TBLPTRH
TBLPTRL
EECON1, FREE
EECON1, WR
a
PIC18F6XJXX/8XJXX
FIGURE 3-3:
Addr = Addr + 1024
Core Instruction
ROW ERASE CODE
MEMORY FLOW
No
Start Erase Sequence
and Hold PGC High
for Time P10
Row Erase
DS39644L-page 15
Device for
Configure
Done?
Rows
Done
Start
All
Yes
Addr = 0