PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 22

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6XJXX/8XJXX
TABLE 5-2:
DS39644L-page 22
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L
300005h CONFIG3H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Implemented in PIC18F6XJ5X/8XJ5X devices only.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally
executed.
This bit should always be maintained as ‘0’.
Implemented in 80-pin devices only. On 64-pin devices, these bits are reserved and should always be maintained as ‘1’.
DEVID registers are read-only and cannot be programmed by the user.
Implemented in PIC18F6XJ5X/8XJ5X and PIC18F66J11/66J16/67J11/86J11/86J16/87J11 only.
Implemented in PIC18F8XJ5X and PIC18F86J11/86J16/87J11 only.
Implemented in PIC18FXXJ10/8XJ15 devices only.
Implemented in PIC18FX79X and PIC18FX6J9X.
Not implemented in PIC18F8XJ9X.
(5)
(5)
CONFIGURATION BITS AND DEVICE IDs
WAIT
DEBUG
DEBUG
DEV10
DEV2
IESO
IESO
Bit 7
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(4,10)
BW
FCMEN
FCMEN
XINST
XINST
DEV1
DEV9
Bit 6
—
—
—
—
—
—
—
(4,10)
(2)
(2)
(2)
(2)
(2)
(2)
EMB1
STVREN
STVREN
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(4,10)
LPT1OSC
EMB0
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(4,10)
(9)
EASHFT
MSSPSEL
MSSPSEL
PLLDIV2
WDTPS3
T1DIG
REV3
DEV6
Bit 3
—
—
—
—
—
—
(3)
(3)
(9)
(4,10)
(1)
(6)
(6)
PLLDIV1
PMPMX
WDTPS2
FOSC2
FOSC2
REV2
DEV5
Bit 2
CP0
CP0
—
—
—
—
—
(7)
(1)
ECCPMX
ECCPMX
ECCPMX
CPUDIV1
PLLDIV0
WDTPS1
RTCOSC
FOSC1
FOSC1
REV1
DEV4
Bit 1
—
—
—
 2009 Microchip Technology Inc.
(4,7,8)
(4,7,8)
(4,7,8)
(1)
(1)
CPUDIV0
WDTPS0
CCP2MX
CCP2MX
CCP2MX
WDTEN
WDTEN
FOSC0
FOSC0
REV0
DEV3
Bit 0
—
—
—
(1)
Unprogrammed
111- ---1
111- 1111
---- 01--
---- 0111
11-- -111
11-1 1111
---- 1111
---- ----
---- --1-
---- --11
---- 1111
---- 1-11
See Table 5-4
See Table 5-4
Default/
Value
(1)
(1)
(7)
(6)