DSPIC30F2010-20E/SP Microchip Technology, DSPIC30F2010-20E/SP Datasheet - Page 17

• Manufacturer Part Number: DSPIC30F2010-20E/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

21. Module: PWM
22. Module: I/O
23. Module: FRC
© 2010 Microchip Technology Inc.
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up as if PTDIR was zero.
Work around
None.
Affected Silicon Revisions
If the user application enables the auto-baud feature
in the UART module, the I/O pin multiplexed with the
IC1 (Input Capture 1) pin cannot be used as a digital
input. However, the external interrupt function
(INT1) can be used.
Work around
None.
Affected Silicon Revisions
Internal FRC accuracy is outside the specification
documented in “Electrical Characteristics”,
Table 22-17 “AC Characteristics: Internal RC
Accuracy” of the “dsPIC30F2010 Data Sheet”
(DS70118).
The actual internal FRC accuracy is:
• ±4% for 25°C
• ±5% for -40°C and 85°C
• ±6% for 125°C
Work around
None.
Affected Silicon Revisions
A0
A0
A0
X
X
X
A1
A1
A1
X
X
X
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
24. Module: I
25. Module: Timer
26. Module: PLL
If there are two I
them acts as the master receiver and the other
acts as the slave transmitter. If both devices are
configured for 10-bit addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, when the slave select address is sent
from the master, both the master and slave
acknowledge it. When the master sends out the
read operation, both the master and the slave
enter into Read mode, and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9, should be different.
Affected Silicon Revisions
When the timer is being operated in Asynchronous
mode using the Secondary Oscillator (32.768 kHz)
and the device is put into Sleep mode, a clock
switch to any other oscillator mode before putting
the device to Sleep prevents the timer from waking
the device from Sleep.
Work around
Do not clock switch to any other oscillator mode if
the timer is being used in Asynchronous mode
using the Secondary Oscillator (32.768 kHz).
Affected Silicon Revisions
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
Work around
The user application must include an oscillator fail-
ure Trap Service Routine. In the Trap Service Rou-
tine, first inspect the status of the Clock Failure
Status bit (OSCCON<3>). If this bit is clear, return
from the Trap Service Routine immediately and
continue program execution.
Affected Silicon Revisions
A0
A0
A0
X
X
X
2
C devices, the addresses, as well as bits
A1
A1
A1
X
X
X
2
dsPIC30F2010
C
A2
A2
A2
X
X
X
2
C devices on the bus, one of
A3
A3
A3
X
X
A4
A4
A4
X
X
DS80451E-page 17