PIC16F1947-I/PT Microchip Technology, PIC16F1947-I/PT Datasheet
PIC16F1947-I/PT
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PIC16F1947-I/PT Summary of contents
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... LCD Driver and nanoWatt XLP Technology 2010 Microchip Technology Inc. PIC16F/LF1946/47 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary DS41414B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology Devices Included In This Data Sheet: • PIC16F1946 • PIC16F1947 • PIC16LF1946 • PIC16LF1947 High-Performance RISC CPU: • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed – 32 MHz oscillator/clock input - DC – ...
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... Software enable hysteresis • Voltage Reference Module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection PIC16F/LF1946/47 Family Types PIC16F1946 8192 256 512 PIC16LF1946 PIC16F1947 16384 256 1024 PIC16LF1947 DS41414B-page 4/1 54 ...
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... SEG21/C1IN2-/C2IN2-/C3IN2-/CPS8/AN8/RF3 SEG20/SRQ/C1OUT/CPS7/AN7/RF2 Note 1: Pin location selected by APFCON register setting. Default location. Pin function can be moved using the APFCON register. Alternate location. 2: QFN package orientation is the same. No leads are present on the QFN package. 3: 2010 Microchip Technology Inc. PIC16F/LF1946/47 PIC16F/LF1946/47 ...
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... SEG0 — — — — SEG1 — — — — SEG2 — — — — SEG3 — — — SDO2 SEG4 — — — SDI2 SEG5 — — — SDA2 SCK2/ SEG6 — — — SCL2 2010 Microchip Technology Inc. ...
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... Note 1: Pin functions can be moved using the APFCON register(s). Default location. Pin function can be moved using the APFCON register. Alternate location. 2: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. 3: See Section 8.0. 4: 2010 Microchip Technology Inc. PIC16F/LF1946/47 — — — — — ...
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... Appendix A: Data Sheet Revision History.......................................................................................................................................... 435 ® Appendix B: Migrating From Other PIC Devices.............................................................................................................................. 435 Index .................................................................................................................................................................................................. 437 The Microchip Web Site ..................................................................................................................................................................... 445 Customer Change Notification Service .............................................................................................................................................. 445 Customer Support .............................................................................................................................................................................. 445 Reader Response .............................................................................................................................................................................. 446 Product Identification System............................................................................................................................................................. 447 DS41414B-page 8 Preliminary 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2010 Microchip Technology Inc. PIC16F/LF1946/47 to receive the most current information on all of our products. Preliminary DS41414B-page 9 ...
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... PIC16F/LF1946/47 NOTES: DS41414B-page 10 Preliminary 2010 Microchip Technology Inc. ...
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... CCP4 CCP5 Comparators EUSARTS EUSART1 EUSART2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2010 Microchip Technology Inc. PIC16F/LF1946/47 of the shows the pin- ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... ECCP2 See applicable chapters for more information on peripherals. Note 1: DS41414B-page 12 Program Flash Memory CPU Figure 2-1 Timer1 Timer2 Timer4 Timer6 MSSPx ECCP3 CCP4 CCP5 Preliminary RAM EEPROM PORTA PORTB PORTC PORTD PORTE PORTF PORTG Comparators EUSARTx 2010 Microchip Technology Inc. ...
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... SEG8 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin function is selectable via the APFCON register. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Input Output Type Type TTL CMOS General purpose I/O. ...
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... LCD Analog output. ST CMOS General purpose I/O. ST — SPI data input C™ data input/output. — AN LCD Analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... VLCD1 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin function is selectable via the APFCON register. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Input Output Type Type ST CMOS General purpose I/O. — ...
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... A/D Channel 7 input. AN — Capacitive sensing input 7. — CMOS Comparator C1 output. — CMOS SR Latch non-inverting output. — AN LCD Analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... SEG43 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin function is selectable via the APFCON register. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Input Output Type Type TTL CMOS General purpose I/O. ...
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... General purpose input. ST — Master Clear with internal pull-up. HV — Programming voltage. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Saving”, for more for more Preliminary DS41414B-page 19 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2010 Microchip Technology Inc. ...
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... Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F/LF1946 PIC16F/LF1947 2010 Microchip Technology Inc. PIC16F/LF1946/47 The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3 ...
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... PIC16F/LF1947 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh Page 4 2000h Page 7 3FFFh 4000h Rollover to Page 0 Rollover to Page 7 7FFFh 2010 Microchip Technology Inc. ...
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... THE CONSTANT The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414B-page 23 ...
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... STATUS • FSR0 Low • FSR0 High • FSR1 Low • FSR1 High • BSR • WREG • PCLATH • INTCON The core registers are the first 12 Note: addresses of every data memory bank. “Indirect Preliminary 2010 Microchip Technology Inc. ...
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... Note 1: second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010 Microchip Technology Inc. PIC16F/LF1946/47 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...
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... The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC16F/LF1946/47 Section 3.5.2 Preliminary MEMORY MAP TABLES Banks Table No. 0-7 Table 3-3 8-15 Table 3-4, Table 3-7 16-23 Table 3-5 23-31 Table 3-6, Table 3-8 2010 Microchip Technology Inc. ...
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TABLE 3-3: PIC16F/LF1946/1947 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
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TABLE 3-4: PIC16F/LF1946/1947 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
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TABLE 3-5: PIC16F/LF1946/47 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
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TABLE 3-6: PIC16F/LF1946/47 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... LCDDATA21 7B6h LCDDATA22 7B7h LCDDATA23 7B8h Unimplemented Read as ‘0’ 7EFh = Unimplemented data memory locations, Legend: read as ‘0’. 2010 Microchip Technology Inc. PIC16F/LF1946/47 TABLE 3-8: PIC16F/LF1946/47 MEMORY MAP, BANK 31 Bank 31 F8Ch ICDIO F8Dh ICDCON0 F8Eh ICDCON1 F8Fh ICDCON2 — ...
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... PIC16F/LF1946/47 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device Bank( PIC16F/LF1946/ 9-14 15 16-30 31 DS41414B-page 32 Page No Preliminary 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... SCS<1:0> 0011 1-00 0011 1-00 LFIOFR HFIOFS 00q0 0q0- qqqq qq0- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... STR1B STR1A ---0 0001 ---0 0001 — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 PSS2BD<1:0> 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C5TSEL<1:0> ---- --00 ---- --00 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... IOCBP1 IOCBP0 0000 0000 0000 0000 IOCBN1 IOCBN0 0000 0000 0000 0000 IOCBF1 IOCBF0 0000 0000 0000 0000 — — — — — — — — — — — — — — — — — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 — — — — — — — — — — — — — — — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... COM0 COM0 SEG17 SEG16 xxxx xxxx uuuu uuuu COM0 COM0 SEG1 SEG0 xxxx xxxx uuuu uuuu COM1 COM1 SEG9 SEG8 xxxx xxxx uuuu uuuu COM1 COM1 SEG17 SEG16 xxxx xxxx uuuu uuuu COM1 COM1 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 ...
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... INTF IOCIF 0000 000x 0000 000u — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2010 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010 Microchip Technology Inc. PIC16F/LF1946/47 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2010 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2010 Microchip Technology Inc. PIC16F/LF1946/47 0x0F Return Address 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41414B-page 52 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2010 Microchip Technology Inc. PIC16F/LF1946/47 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary ...
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... FIGURE 3-12: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2010 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2010 Microchip Technology Inc. PIC16F/LF1946/47 by device Preliminary DS41414B-page 55 ...
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... Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit pin function is MCLR; Weak pull-up enabled. pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2010 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414B-page 57 ...
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... R/P-1/1 U-1 U-1 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) must be used for programming PP pin Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2010 Microchip Technology Inc. ...
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... See Section 4.5 “Device ID and Revision ID” information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F193X/LF193X/PIC16F194X/LF194X Memory Programming Specification” (DS41397). 2010 Microchip Technology Inc. PIC16F/LF1946/47 “Write such as for more ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100011001 = PIC16F1946 100011010 = PIC16F1947 100011011 = PIC16LF1946 100011100 = PIC16LF1947 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: ...
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... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010 Microchip Technology Inc. PIC16F/LF1946/47 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
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... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2010 Microchip Technology Inc. ...
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... Configuration Word 1: • High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101) 2010 Microchip Technology Inc. PIC16F/LF1946/47 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL Specifications in Section 30.0 2010 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. 2010 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...
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... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables of Specifications” Preliminary 2010 Microchip Technology Inc. Figure 5-7). If this is the Table 5-1. Section 30.0 “Electrical ...
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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2010 Microchip Technology Inc. PIC16F/LF1946/47 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more 2010 Microchip Technology Inc. ...
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... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary 2010 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
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... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41414B-page 74 Oscillator Failure Test Test Preliminary Failure Detected Test 2010 Microchip Technology Inc. ...
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... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Section 5.2.2.1 “ ...
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... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41414B-page 76 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 2010 Microchip Technology Inc. ...
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... PIE2 OSFIE C2IE OSFIF C2IF PIR2 T1CON TMR1CS<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend: PIC16F1947 only. Note 1: TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Name Bits Bit -/7 Bit -/6 13:8 — — ...
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... PIC16F/LF1946/47 NOTES: DS41414B-page 78 Preliminary 2010 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010 Microchip Technology Inc. PIC16F/LF1946/47 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41414B-page 79 ...
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... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake-up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2010 Microchip Technology Inc. ...
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... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2010 Microchip Technology Inc. PIC16F/LF1946/47 T BORRDY BOR Protection Active (1) T PWRT < T ...
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... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 6-4 for Preliminary Timer configuration. See for more information. Figure 6-4). This 2010 Microchip Technology Inc. ...
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... FIGURE 6-4: RESET START-UP SEQUENCE V DD Internal POR Power Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010 Microchip Technology Inc. PIC16F/LF1946/47 T PWRT T MCLR T OST Preliminary DS41414B-page 83 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2010 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC16F/LF1946/47 6-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41414B-page 86 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 81 POR BOR SWDTEN 109 2010 Microchip Technology Inc. ...
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... A block diagram of the interrupt logic is shown in Figure 7-1 and Figure 7-2. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 7-2) 2010 Microchip Technology Inc. PIC16F/LF1946/47 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Preliminary Interrupt to CPU DS41414B-page 87 ...
Page 88
... CCP5IF CCP5IE OSFIF OSFIE TMR1IF TMR1IE TMR6IF TMR6IE C2IF C2IE C1IF C1IE EEIF EEIE BCLIF BCLIE LCDIF LCDIE DS41414B-page 88 Preliminary 2010 Microchip Technology Inc. To Interrupt Logic (Figure 7-1) ...
Page 89
... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010 Microchip Technology Inc. PIC16F/LF1946/47 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 90
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2010 Microchip Technology Inc. ...
Page 91
... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010 Microchip Technology Inc. PIC16F/LF1946/ ...
Page 92
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41414B-page 92 Preliminary 2010 Microchip Technology Inc. ...
Page 93
... None of the interrupt-on-change pins have changed state The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register Note 1: have been cleared by software. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Interrupt flag bits are set when an interrupt Note: ...
Page 94
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2010 Microchip Technology Inc. ...
Page 95
... Enables the Comparator C3 interrupt 0 = Disables the Comparator C3 interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 ...
Page 96
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0 2010 Microchip Technology Inc. ...
Page 97
... Disables the MSSP2 Bus Collision Interrupt bit 0 SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
Page 98
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2010 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 99
... Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2010 Microchip Technology Inc. PIC16F/LF1946/47 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 100
... R/W-0/0 R/W-0/0 R/W-0/0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the R/W-0/0 R/W-0/0 TMR4IF — bit 0 2010 Microchip Technology Inc. ...
Page 101
... Interrupt is not pending bit 0 SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2010 Microchip Technology Inc. PIC16F/LF1946/47 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 102
... CCP4IF CCP3IF TMR6IF — RC2IF TX2IF — — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 93 PS<2:0> 195 TMR2IE TMR1IE 94 C3IE CCP2IE 95 TMR4IE — 96 BCL2IE SSP2IE 97 TMR2IF TMR1IF 98 C3IF CCP2IF 99 TMR4IF — 100 BCL2IF SSP2IF 101 2010 Microchip Technology Inc. ...
Page 103
... Shaded cells are not used by LDO. Legend: 2010 Microchip Technology Inc. PIC16F/LF1946/47 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...
Page 104
... PIC16F/LF1946/47 NOTES: DS41414B-page 104 Preliminary 2010 Microchip Technology Inc. ...
Page 105
... Section 17.0 “Digital-to-Analog Con- and verter (DAC) Module” Section 14.0 “Fixed Volt- for more information on these age Reference (FVR)” modules. 2010 Microchip Technology Inc. PIC16F/LF1946/47 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. ...
Page 106
... Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 93 IOCBF1 IOCBF0 152 IOCBN1 IOCBN0 152 IOCBP1 IOCBP0 152 TMR2IE TMR1IE 94 C3IE CCP2IE 95 TMR4IE — 96 BCL2IE SSP2IE 97 TMR2IF TMR1IF 98 C3IF CCP2IF 99 TMR4IF — 100 BCL2IF SSP2IF 101 SWDTEN 109 2010 Microchip Technology Inc. ...
Page 107
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010 Microchip Technology Inc. PIC16F/LF1946/47 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41414B-page 107 ...
Page 108
... STATUS register are changed to indicate the event. See Active Section 3.0 “Memory Organization” Active register (Register 3-1) for more information. Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and STATUS WDT Cleared Cleared until the end of OST Unaffected 2010 Microchip Technology Inc. ...
Page 109
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 110
... PIC16F/LF1946/47 NOTES: DS41414B-page 110 Preliminary 2010 Microchip Technology Inc. ...
Page 111
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010 Microchip Technology Inc. PIC16F/LF1946/47 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 112
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2010 Microchip Technology Inc. (Register 4-1) ...
Page 113
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010 Microchip Technology Inc. PIC16F/LF1946/47 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 114
... NOPs. This prevents the user from executing a two-cycle instruction instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Write Latches/Boundary 8 words, EEADRL<2:0> = 000 Preliminary 2010 Microchip Technology Inc. on the next ...
Page 115
... NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010 Microchip Technology Inc. PIC16F/LF1946/47 (Figure 11-1) (Figure 11-1) Preliminary DS41414B-page 115 ...
Page 116
... EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. The code Note: Example 11-5 times to fully program an erased program memory row. Preliminary 2010 Microchip Technology Inc. 11-5. The initial address is sequence provided in must be repeated multiple ...
Page 117
... EEADRL<3:0> = 0000 EEADRL<3:0> = 0001 Buffer Register 2010 Microchip Technology Inc. PIC16F/LF1946/47 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 118
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 119
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010 Microchip Technology Inc. PIC16F/LF1946/47 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 120
... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No 2010 Microchip Technology Inc. ...
Page 121
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414B-page 121 ...
Page 122
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2010 Microchip Technology Inc. ...
Page 123
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 124
... EEADRL<7:0> EEADRH<6:0> EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCLIE LCDIE C1IF EEIF BCLIF LCDIF Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page WR RD 123 111* 122 122 122 122 INTF IOCIF 93 C3IE CCP2IE 95 C3IF CCP2IF 99 2010 Microchip Technology Inc. ...
Page 125
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register ...
Page 126
... P1BSEL: CCP1 PWM B Output Pin Selection bit 0 = P1B function is on RE6/P1B/COM3 1 = P1B function is on RD6/P1B/SEG6 DS41414B-page 126 R/W-0/0 R/W-0/0 R/W-0/0 P2CSEL P2BSEL CCP2SEL U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 P1CSEL P1BSEL bit 0 2010 Microchip Technology Inc. ...
Page 127
... MOVLW B'11110000' ;Set RA<7:4> as inputs MOVWF TRISA ;and set RA<3:0> as ;outputs 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet ...
Page 128
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2010 Microchip Technology Inc. ...
Page 129
... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend: 2010 Microchip Technology Inc. PIC16F/LF1946/47 U-0 R/W-1/1 — ANSA3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 130
... SEG8 (LCD) RB2 1. SEG9 (LCD) RB3 1. SEG10 (LCD) RB4 1. SEG11 (LCD) RB5 1. SEG29 (LCD) 2. T1G (TMR1) RB6 Section 13.0 1. ICSPCLK (Programming) 2. ICDCLK (enabled by Configuration Word) 3. SEG38 (LCD) RB7 1. ICSPDAT (Programming) 2. ICDDAT (enabled by Configuration Word) 3. SEG39 (LCD) Preliminary 2010 Microchip Technology Inc. ...
Page 131
... Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u RB4 RB3 RB2 U = Unimplemented bit, read as ‘ ...
Page 132
... IOCBF1 IOCBF0 152 LATB2 LATB1 LATB0 131 SE10 SE9 SE8 341 SE26 SE25 SE24 341 SE34 SE33 SE32 341 PS<2:0> 195 RB2 RB1 RB0 131 T1GSS<1:0> 206 TRISB2 TRISB1 TRISB0 131 WPUB2 WPUB1 WPUB0 132 2010 Microchip Technology Inc. ...
Page 133
... TRISC ; MOVLW B'11110000' ;Set RC<7:4> as inputs MOVWF TRISC ;and set RC<3:0> as ;outputs 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The is TRISC pins, their combined functions and their output priorities are briefly described here ...
Page 134
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0 2010 Microchip Technology Inc. ...
Page 135
... TMR1CS<1:0> TX1STA CSRC TX9 TX2STA CSRC TX9 TRISC TRISC7 TRISC6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 P2DSEL P2CSEL P2BSEL CCP2SEL LATC5 LATC4 LATC3 ...
Page 136
... P2B (CCP) 2. SEG2 (LCD) RD3 1. SEG3 (LCD) 2. P3C (CCP) RD4 1. SEG4 (LCD) 2. P3D (CCP) 3. SDO2 (SSP2) RD5 1. SEG5 (LCD) 2. P1C (CCP) 3. SDI2/SDA2 (SSP2) RD6 1. SEG5 (LCD) 2. P1B (CCP) 3. SCK2/SCL2 (SSP2) RD7 1. SEG7 (LCD) 2. SS2 (SSP2) Preliminary 2010 Microchip Technology Inc. ...
Page 137
... Bit is cleared bit 7-0 LATD<7:0>: PORTD Output Latch Value bits Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is Note 1: return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u RD4 RD3 RD2 U = Unimplemented bit, read as ‘ ...
Page 138
... CS<1:0> SE5 SE4 SE3 SE2 RD5 RD4 RD3 RD2 TRISD5 TRISD4 TRISD3 TRISD2 Preliminary Register on Bit 1 Bit 0 Page P1CSEL P1BSEL 126 236 LATD1 LATD0 137 LMUX<1:0> 337 SE1 SE0 341 RD1 RD0 137 TRISD1 TRISD0 137 2010 Microchip Technology Inc. ...
Page 139
... MOVLW B‘00001100’ ;Set RE<3:2> as inputs MOVWF TRISE ;and set RE<1:0> ;as outputs 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet ...
Page 140
... Value at POR and BOR/Value at all other Resets R/W-1 R/W-1 R/W-1 TRISE4 TRISE3 TRISE2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u RE1 RE0 bit 0 R/W-1 R/W-1 TRISE1 TRISE0 bit 0 2010 Microchip Technology Inc. ...
Page 141
... TRISE TRISE7 TRISE6 x = unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Legend: Applies to ECCP modules only. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u LATE4 LATE3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 142
... CLRF PORTF ;Init PORTF BANKSEL LATF ;Data Latch CLRF LATF ; BANKSEL ANSELF ; CLRF ANSELF ;digital I/O BANKSEL TRISF ; MOVLW B'11110000' ;Set RF<7:4> as inputs MOVWF TRISF ;and set RF<3:0> as ;outputs DS41414B-page 142 is TRISF 12-13) reads the Preliminary 2010 Microchip Technology Inc. ...
Page 143
... SRQ (SR Latch) RF3 1. AN8 (ADC) 2. CPS8 (CSM) 3. C123IN2- (Comparator) 4. SEG21 (LCD) RF4 1. AN9 (ADC) 2. CPS9 (CSM) 3. C2IN+ (Comparator) 4. SEG22 (LCD) 2010 Microchip Technology Inc. PIC16F/LF1946/47 RF5 1. AN10 (ADC) 2. CPS10 (CSM) 3. C12IN1- (Comparator) 4. DACOUT (DAC) 5. SEG23 (LCD) RF6 1. AN11 (ADC) 2. CPS11 (CSM) 3. ...
Page 144
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATF4 LATF3 LATF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RF1 RF0 bit 0 R/W-1/1 R/W-1/1 TRISF1 TRISF0 bit 0 R/W-x/u R/W-x/u LATF1 LATF0 bit 0 2010 Microchip Technology Inc. ...
Page 145
... CONFIG2 7:0 — — — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend: 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-1/1 ANSDF4 ANSF3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 146
... C3IN+ (Comparator) 5. SEG44 (LCD) RG3 1. AN13 (ADC) 2. CPS13 (CSM) 3. C3IN0- (Comparator) 4. CCP4 (CCP) 5. P3D (CCP) 6. SEG45 (LCD) RG4 1. AN12 (ADC) 2. CPS12 (CSM) 3. C3IN1- (Comparator) 4. CCP5 (CCP) 5. P1D (CCP) 6. SEG26 (LCD) RG5 1. V /MCLR (Basic)SEG18 (LCD) PP Preliminary 2010 Microchip Technology Inc. ...
Page 147
... Unimplemented: Read as ‘0’. bit 5-0 LATG<5:0>: PORTG Output Latch Value bits Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual Note 1: I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u RG4 RG3 RG2 U = Unimplemented bit, read as ‘ ...
Page 148
... Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-1/1 U-0 ANSG1 — bit 0 U-0 U-0 — — bit 0 2010 Microchip Technology Inc. ...
Page 149
... TRISG WPUG — — unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTG. Legend: Applies to ECCP modules only. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — ANSG4 ANSG3 ANSG2 DCxB< ...
Page 150
... PIC16F/LF1946/47 NOTES: DS41414B-page 150 Preliminary 2010 Microchip Technology Inc. ...
Page 151
... R RBx IOCBPx 2010 Microchip Technology Inc. PIC16F/LF1946/47 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 152
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2010 Microchip Technology Inc. ...
Page 153
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF IOCBF5 IOCBF4 IOCBF3 ...
Page 154
... PIC16F/LF1946/47 NOTES: DS41414B-page 154 Preliminary 2010 Microchip Technology Inc. ...
Page 155
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010 Microchip Technology Inc. PIC16F/LF1946/47 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 156
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (3) (3) (High Range) (Low Range for additional information. Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> Preliminary R/W-0/0 R/W-0/0 ADFVR<1:0> bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR<1:0> 156 2010 Microchip Technology Inc. ...
Page 157
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010 Microchip Technology Inc. PIC16F/LF1946/47 FIGURE 15-1: 15.2 Minimum Operating V ...
Page 158
... PIC16F/LF1946/47 NOTES: DS41414B-page 158 Preliminary 2010 Microchip Technology Inc. ...
Page 159
... The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. 2010 Microchip Technology Inc. PIC16F/LF1946/47 (ADC) allows Preliminary DS41414B-page 159 ...
Page 160
... ADPREF = 00 ADPREF = ADPREF = 10 REF 00000 00001 00010 00011 00100 00101 00110 00111 ADC 01000 01001 GO/DONE 01010 01011 01100 ADON 01101 V SS 01110 01111 10000 11101 11110 11111 Preliminary Left Justify ADFM 1 = Right Justify 16 ADRESH ADRESL 2010 Microchip Technology Inc. ...
Page 161
... V SS See Section 14.0 “Fixed Voltage Reference (FVR)” for more details on the fixed voltage reference. 2010 Microchip Technology Inc. PIC16F/LF1946/47 16.1.4 CONVERSION CLOCK The source of the conversion clock is software select- able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • ...
Page 162
... 2010 Microchip Technology Inc. ...
Page 163
... MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC16F/LF1946/47 16.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. ...
Page 164
... PIC16F/LF1946/47 Using the Special Event Trigger does not assure proper ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. Refer to Section 23.0 “Capture/Compare/PWM for more information. Modules” Preliminary 2010 Microchip Technology Inc. RC CCPx/ECCPx CCP5 ...
Page 165
... Sleep and resume in-line code execution. 2: Refer to Section 16.3 “A/D Acquisition Requirements”. 2010 Microchip Technology Inc. PIC16F/LF1946/47 EXAMPLE 16-1: ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ...
Page 166
... Section 15.0 “Temperature Indicator Module” DS41414B-page 166 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (2) for more information. for more information. for more information. Preliminary R/W-0/0 R/W-0/0 GO/DONE ADON bit 0 2010 Microchip Technology Inc. ...
Page 167
... V REF connected to internal Fixed Voltage Reference (FVR) module REF When selecting the FVR or the V Note 1: minimum voltage specification exists. See 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-0/0 U-0 R/W-0/0 — ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u — — bit 0 2010 Microchip Technology Inc. ...
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... W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u — — — Unimplemented bit, read as ‘0’ ...
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... HOLD Preliminary Equation 16-1 may be 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED 2010 Microchip Technology Inc. ...
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... Sampling Switch V = Threshold Voltage T Refer to Note 1: Section 30.0 “Electrical Specifications” FIGURE 16-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 03h 02h 01h 00h V - REF 2010 Microchip Technology Inc. PIC16F/LF1946/ Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. ...
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... ADPREF<1:0> 167 168 168 ANSA1 ANSA0 129 ANSELF1 ANSELF0 145 ANSELG1 — 148 CCP1M<3:0> 236 INTF IOCIF 93 TMR2IE TMR1IE 94 TMR2IF TMR1IF 98 TRISA1 TRISA0 128 TRISB1 TRISB0 131 TRISE1 TRISE0 140 ADFVR<1:0> 156 — DACNSS 176 176 2010 Microchip Technology Inc. ...
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... The value of the individual resistors within the ladder can be found in Section 30.0 Specifications”. 2010 Microchip Technology Inc. PIC16F/LF1946/47 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. ...
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... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41414B-page 174 Digital-to-Analog Converter (DAC) V SOURCE + Steps SOURCE - + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator and ADC Modules) DACOUT DACOE Buffered DAC Output 2010 Microchip Technology Inc. ...
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... DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2010 Microchip Technology Inc. PIC16F/LF1946/47 This is also the method used to output the voltage level from the FVR to an output pin. See “ ...
Page 176
... Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> DACOE — DACPSS<1:0> — DACR<4:0> Preliminary U-0 R/W-0/0 — DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0 Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 156 — DACNSS 176 176 2010 Microchip Technology Inc. ...
Page 177
... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2010 Microchip Technology Inc. PIC16F/LF1946/47 FIGURE 18- ...
Page 178
... Output of comparator can be frozen during debugging. 3: DS41414B-page 178 (1) Interrupt Interrupt C POL ( CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2010 Microchip Technology Inc. ...
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... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2010 Microchip Technology Inc. PIC16F/LF1946/47 18.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The ...
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... Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 17.0 “Digital-to-Analog for more information on the DAC input (DAC) Module” signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. Preliminary 2010 Microchip Technology Inc. Converter ...
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... ECCP Auto-Shutdown mode. 2010 Microchip Technology Inc. PIC16F/LF1946/47 18.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-3 ...
Page 182
... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 “Electrical Specifications” DS41414B-page 182 V DD 0. (1) LEAKAGE 0. Vss Preliminary To Comparator 2010 Microchip Technology Inc. ...
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... CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-0/0 U-0 R/W-1/1 ...
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... IN0- pin X IN1- pin X IN2- pin X IN3- pin X U-0 U-0 R-0/0 MC3OUT — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxNCH<1:0> bit 0 R-0/0 R-0/0 MC2OUT MC1OUT bit 0 2010 Microchip Technology Inc. ...
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... C2IE PIR2 OSFIF C2IF TRISF TRISF7 TRISF6 TRISG — — — = unimplemented location, read as ‘0’. Shaded cells are unused by the Comparator module. Legend: 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 ANSF5 ANSF4 ANSF3 ANSF2 — ANSG4 ANSG3 ...
Page 186
... PIC16F/LF1946/47 NOTES: DS41414B-page 186 Preliminary 2010 Microchip Technology Inc. ...
Page 187
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2010 Microchip Technology Inc. PIC16F/LF1946/47 19.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
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... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41414B-page 188 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2010 Microchip Technology Inc. SRQ SRNQ ...
Page 189
... Pulse set input for 1 Q-clock period effect on set input bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input Set only, always reads back ‘ 0 ’. Note 1: 2010 Microchip Technology Inc. PIC16F/LF1946/ MHz MHz OSC OSC 39 ...
Page 190
... C1 Comparator output has no effect on the reset input of the SR Latch DS41414B-page 190 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2010 Microchip Technology Inc. ...
Page 191
... SRCON0 SRLEN SRCLK<2:0> SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR Latch module. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 ANSA5 — ANSA3 ANSA2 SRQEN SRNQEN ...
Page 192
... PIC16F/LF1946/47 NOTES: DS41414B-page 192 Preliminary 2010 Microchip Technology Inc. ...
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... From CPSCLK 1 TMR0CS TMR0SE T0XCS 2010 Microchip Technology Inc. PIC16F/LF1946/47 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register Note: can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...
Page 194
... Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41414B-page 194 Preliminary 2010 Microchip Technology Inc. ...
Page 195
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 196
... PIC16F/LF1946/47 NOTES: DS41414B-page 196 Preliminary 2010 Microchip Technology Inc. ...
Page 197
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010 Microchip Technology Inc. PIC16F/LF1946/47 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...
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... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2010 Microchip Technology Inc. ...
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... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010 Microchip Technology Inc. PIC16F/LF1946/47 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
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... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary Figure 21-6 for 2010 Microchip Technology Inc. ...