PIC16LF707-I/P Microchip Technology, PIC16LF707-I/P Datasheet - Page 158
![MCU 8BIT 14KB FLASH 5.5V 40PDIP](/photos/19/6/190627/4696013_sml.jpg)
PIC16LF707-I/P
Manufacturer Part Number
PIC16LF707-I/P
Description
MCU 8BIT 14KB FLASH 5.5V 40PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF707-I/P
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
36
Program Memory Type
FLASH
Ram Size
363 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16LF
No. Of I/o's
36
Ram Memory Size
363Byte
Cpu Speed
20MHz
No. Of Timers
6
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 14 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF707-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16F707/PIC16LF707
FIGURE 19-2:
DS41418A-page 158
RA0/SS
RA5/SS
SCK
SDO
SDI
Select
Edge
TRISx
Read
bit 0
Select
SPI MODE BLOCK
DIAGRAM
Clock Select
Edge
SSPBUF Reg
SSSEL
2
SSPSR Reg
SSPM<3:0>
4
Clock
Shift
SS
Control
Enable
bit 7
2
Prescaler
4, 16, 64
Write
Data Bus
Internal
TMR2
Output
F
OSC
Preliminary
19.1.1
In Master mode, data transfer can be initiated at any
time because the master controls the SCK line. Master
mode determines when the slave (Figure 19-1,
Processor 2) transmits data via control of the SCK line.
19.1.1.1
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
register shifts the data in and out of the device, MSb
first. The SSPBUF register holds the data that is written
out of the master until the received data is ready. Once
the eight bits of data have been received, the byte is
moved to the SSPBUF register. The Buffer Full Status
bit, BF of the SSPSTAT register, and the SSP Interrupt
Flag bit, SSPIF of the PIR1 register, are then set.
Any write to the SSPBUF register during transmission/
reception of data will be ignored and the Write Collision
Detect bit, WCOL of the SSPCON register, will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
register completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data is written to the SSPBUF. The BF bit of the
SSPSTAT register is set when SSPBUF has been
loaded with the received data (transmission is
complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. The SSP interrupt may be used to
determine
complete and the SSPBUF must be read and/or
written. If interrupts are not used, then software polling
can be done to ensure that a write collision does not
occur. Example 19-1 shows the loading of the SSPBUF
(SSPSR) for data transmission.
19.1.1.2
To enable the serial port, the SSPEN bit of the
SSPCON register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON register and then set the SSPEN bit. If a
Master mode of operation is selected in the SSPM bits
of the SSPCON register, the SDI, SDO and SCK pins
will be assigned as serial port pins.
For these pins to function as serial port pins, they must
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as output
Note:
MASTER MODE
The SSPSR is not directly readable or
writable and can only be accessed by
addressing the SSPBUF register.
when
Master Mode Operation
Enabling Master I/O
the
2010 Microchip Technology Inc.
transmission/reception
is
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