ATMEGA324PA-AUR Atmel, ATMEGA324PA-AUR Datasheet - Page 214
ATMEGA324PA-AUR
Manufacturer Part Number
ATMEGA324PA-AUR
Description
MCU AVR 32KB FLASH 20 MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA324PA-AUR.pdf
(468 pages)
Specifications of ATMEGA324PA-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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8152G–AVR–11/09
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 20-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
Synchronized
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
ATmega164PA/324PA/644PA/1284P
Arbitration, SDA
Master A Loses
A
SDA
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