PIC16LC72A-04/SO Microchip Technology, PIC16LC72A-04/SO Datasheet - Page 64

• Manufacturer Part Number: PIC16LC72A-04/SO
• Description: IC MCU OTP 2KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC72A-04/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16C62B/72A
10.12
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. The WDT will run, even if the
clock on the OSC1/CLKIN and OSC2/CLKOUT pins of
the device has been stopped, for example, by execution
of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 10.1).
FIGURE 10-8: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 10-9: SUMMARY OF WATCHDOG TIMER REGISTERS
DS35008B-page 64
Address
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
Watchdog Timer (WDT)
Name
Config. bits
OPTION_REG
WDT Timer
Enable Bit
WDT
RBPU
Bit 7
From TMR0 Clock Source
(Figure 4-2)
INTEDG
BODEN
Bit 6
0
1
PSA
M
U
X
Preliminary
T0CS
Bit 5
CP1
T0SE
The WDT time-out period (T
multiplied by the prescaler ratio, when the prescaler is
assigned to the WDT. The prescaler assignment
(assigned to either the WDT or Timer0) and prescaler
ratio are set in the OPTION_REG register.
.
Bit 4
CP0
0
Note:
Note:
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
PWRTE
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
Bit 3
PSA
8
PSA
To TMR0 (Figure 4-2)
WDTE
Bit 2
PS2
1999 Microchip Technology Inc.
PS2:PS0
WDT
, parameter #31) is
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0