PIC18F47J53T-I/ML Microchip Technology, PIC18F47J53T-I/ML Datasheet - Page 155

• Manufacturer Part Number: PIC18F47J53T-I/ML
• Description: IC MCU 8BIT 128KB FLASH 44 QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F47J53T-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.5
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or output.
 2010 Microchip Technology Inc.
Note:
Note:
PORTD, TRISD and LATD
Registers
PORTD is available only in 44-pin devices.
On a POR, these pins are configured as
digital inputs.
Preliminary
PIC18F47J53 FAMILY
EXAMPLE 10-5:
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, RDPU (TRISE<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from, a discrete resistor. On an unloaded I/O pin the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
V
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
CLRF
CLRF
MOVLW 0CFh
MOVWF TRISD
DD
levels.
PORTD
LATD
;
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
;
;
INITIALIZING PORTD
Initialize PORTD by
RD<5:4> as outputs
RD<7:6> as inputs
DS39964B-page 155