PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 23

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3
A Configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading Configuration data.
4.4
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADRH:EEADR) and a
Data Latch (EEDATA). Data EEPROM is read by loading
EEADRH:EEADR with the desired memory location and
initiating a memory read by appropriately configuring the
EECON1 register. The data will be loaded into EEDATA,
where it may be serially output on PGD via the 4-bit com-
mand, ‘0010’ (Shift Out Data Holding register). A delay
of P6 must be introduced after the falling edge of the 8th
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low (see Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.
TABLE 4-2:
© 2009 Microchip Technology Inc.
Step 1: Direct access to data EEPROM.
Step 2: Set the Data EEPROM Address Pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
4-Bit
Verify Configuration Bits
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
9E A6
9C A6
0E <Addr>
6E A9
OE <AddrH>
6E AA
80 A6
50 A8
6E F5
00 00
<MSB><LSB>
READ DATA EEPROM MEMORY
Data Payload
BCF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
MOVF
MOVWF
NOP
Shift Out Data
EECON1, EEPGD
EECON1, CFGS
<Addr>
EEADR
<AddrH>
EEADRH
EECON1, RD
EEDATA, W, 0
TABLAT
(1)
FIGURE 4-3:
Core Instruction
PIC18F1230/1330
No
Move to TABLAT
Shift Out Data
READ DATA EEPROM
FLOW
Address
Done?
Read
Done
Start
Byte
Set
Yes
DS39752B-page 23