PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 7

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In addition to the code memory space, there are three
blocks in the Configuration and ID space that are
accessible to the user through table reads and table
writes. Their locations in the memory map are shown in
Figure 2-6.
Users may store identification information (ID) in eight ID
registers. These ID registers are mapped in addresses,
200000h through 200007h. The ID locations read out
normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the Configuration bits. These bits select various device
options and are described in Section 5.0 “Configura-
tion Word”. These Configuration bits read out normally,
even after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
Device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.0 “Configuration
Word”. These Device ID bits read out normally, even
after code protection.
FIGURE 2-6:
© 2009 Microchip Technology Inc.
Note:
2FFFFFh
000000h
01FFFFh
1FFFFFh
3FFFFFh
Sizes of memory areas are not to scale.
Unimplemented
Code Memory
Configuration
Read as ‘0’
and ID
Space
CONFIGURATION AND ID LOCATIONS FOR THE PIC18F1230/1330 DEVICES
2.3.1
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three pointer registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
Addr[21:16]
TBLPTRU
PIC18F1230/1330
MEMORY ADDRESS POINTER
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
ID Location 6
ID Location 7
ID Location 8
TBLPTRH
Addr[15:8]
CONFIG1H
CONFIG2H
CONFIG3H
CONFIG4H
CONFIG5H
CONFIG6H
CONFIG7H
Device ID 1
Device ID 2
CONFIG1L
CONFIG2L
CONFIG3L
CONFIG4L
CONFIG5L
CONFIG6L
CONFIG7L
DS39752B-page 7
3FFFFEh
3FFFFFh
30000Ah
30000Bh
30000Ch
30000Dh
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
300008h
300009h
TBLPTRL
Addr[7:0]