ATMEGA8U2-AU Atmel, ATMEGA8U2-AU Datasheet - Page 177
ATMEGA8U2-AU
Manufacturer Part Number
ATMEGA8U2-AU
Description
MCU AVR 8K FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8U2-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, USB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8U2-AU
Manufacturer:
Atmel
Quantity:
2 772
Part Number:
ATMEGA8U2-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Table 19-1.
19.4
Table 19-2.
7799D–AVR–11/10
Operating Mode
Synchronous Master mode
UCPOLn
SPI Data Modes and Timing
0
0
1
1
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
UCPHAn
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.
0
1
0
1
BAUD
f
UBRRn
OSC
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
XCK
XCK
Data sample (RXD)
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Equation for Calculating Baud Rate
Figure
BAUD
19-1. Data bits are shifted out and latched in on opposite edges of the XCKn
SPI Mode
=
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
2
3
UCPOL=0
-------------------------------------- -
2 UBRRn
(
19-2. Note that changing the setting of any of these bits will corrupt
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
(1)
ATmega8U2/16U2/32U2
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Equation for Calculating UBRRn Value
UBRRn
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Trailing Edge
UCPOL=1
=
------------------- - 1
2BAUD
f
OSC
–
177
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