ATMEGA8U2-AU Atmel, ATMEGA8U2-AU Datasheet - Page 221
ATMEGA8U2-AU
Manufacturer Part Number
ATMEGA8U2-AU
Description
MCU AVR 8K FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8U2-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, USB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8U2-AU
Manufacturer:
Atmel
Quantity:
2 772
Part Number:
ATMEGA8U2-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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21.18.17 UEDATX – USB Data Endpoint Register
21.18.18 UEBCLX – USB Endpoint Byte Count Register
7799D–AVR–11/10
• Bit 3 – RXSTPE: Received SETUP Interrupt Enable Flag
Writing this bit to one enables interrupt on RXSTPI flag. A receiveD setup interrupt will be gener-
ated only if the RXSTPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the RXSTPI is set.
• Bit 2 – RXOUTE: Received OUT Data Interrupt Enable Flag
Writing this bit to one enables interrupt on RXOUTI flag. A receiveD OUT interrupt will be gener-
ated only if the RXOUTE bit is set to one, the Global Interrupt Flag in SREG is written to one,
and the RXOUTI is set.
• Bit 1 – STALLEDE: Stalled Interrupt Enable Flag
Writing this bit to one enables interrupt on STALLEDI flag. A sent STALL interrupt will be gener-
ated only if the STALLEDE bit is set to one, the Global Interrupt Flag in SREG is written to one,
and the STALLEDI is set.
• Bit 0 – TXINE: Transmitter Ready Interrupt Enable Flag
Writing this bit to one enables interrupt on TXINI flag. A transmitter ready interrupt will be gener-
ated only if the TXINE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the TXINI is set.
• Bits 7:0 – DAT[7:0]: Data Bits
The USB Data Endpoint register is a read/write register used for data transfer between the Reg-
ister File and the USB device controller. Writing to the register pushes the data byte into the
current bank of the selected endpoint. Reading the register pops extracts one data byte from the
current bank of the selected endpoint.
• Bits 7:0 – BYCT[7:0]:Byte Count Bits
This register is read only. Its content is updated by the USB controller.
This register contains the number of byte currently loaded into the current bank of the selected
endpoint. The content of this register is incremented after each write access to the endpoint data
register.
Bit
(0xF2)
Read/Write
Initial Value
Bit
(0xF1)
Read/Write
Initial Value
• For IN endpoint:
• For OUT endpoint:
BYCT D7
DAT D7
R/W
R
7
0
7
0
BYCT D6
DAT D6
R/W
R
6
0
6
0
BYCT D5
DAT D5
R/W
5
0
R
5
0
BYCT D4
DAT D4
R/W
4
0
R
4
0
BYCT D3
DAT D3
ATmega8U2/16U2/32U2
R/W
3
0
R
3
0
BYCT D2
DAT D2
R/W
2
0
R
2
0
BYCT D1
DAT D1
R/W
1
0
R
1
0
DAT D0
BYCT D0
R/W
0
0
R
0
0
UEDATX
UEBCLX
R
221
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