DSPIC30F3013-20E/ML Microchip Technology, DSPIC30F3013-20E/ML Datasheet - Page 7
![IC DSPIC MCU/DSP 24K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3013-20E/ML
Manufacturer Part Number
DSPIC30F3013-20E/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(6 pages)
4.DSPIC30F2011-20IP.pdf
(26 pages)
5.DSPIC30F3012-20ISO.pdf
(14 pages)
6.DSPIC30F3012-20ISO.pdf
(20 pages)
Specifications of DSPIC30F3013-20E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register 35-3:
© 2008 Microchip Technology Inc.
Upper Byte:
bit 15
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
FRMEN: Framed SPI1 Support bit
1 = Framed SPI1 support is enabled (SS1 pin is used as frame sync pulse input/output)
0 = Framed SPI1 support is disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application
Legend:
R = Readable bit
-n = Value at POR
SPIFSD
R/W-0
SPI1CON2: SPI1 Control Register 2
Lower Byte:
bit 7
Section 35. Serial Peripheral Interface (SPI) (Part II)
U-0
—
FRMPOL
R/W-0
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
x = Bit is unknown
bit 8
FRMDLY
R/W-0
DS70272B-page 35-7
U-0
—
bit 0
35