PIC18F85J90-I/PT Microchip Technology, PIC18F85J90-I/PT Datasheet - Page 19

• Manufacturer Part Number: PIC18F85J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F85J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 67
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3
TABLE 3-1:
© 2009 Microchip Technology Inc.
CALIBRATION REGISTERS
Address
0x0CC
0x00C
0x0BE
0x0C0
0x0C4
0x0D4
0x0DA
0x0FE
0x13C
0x17C
0x1AA
0x1AB
0x1AC
0x1AD
0x1AE
0x000
0x002
0x004
0x006
0x008
0x00A
0x00E
0x04F
0x064
0x076
0x0A0
0x0B2
0x100
0x108
0x116
0x11A
0x13E
0x13F
0x140
0x143
0x170
0x182
0x194
0x19A
0x1A0
0x1A4
0x1A6
0x1B0
0x1B2
0x1B8
COMPLETE REGISTER LIST
ENERGY_VAR_GLSB
ENERGY_W_L_RAW
PHA_CAL_STATUS
ENERGY_W_GLSB
CF_PULSE_WIDTH
CREEP_THRESH
ENERGY_VAR_Z
ENERGY_VAR_L
PHA_VAR_GLSB
PHA_VAR_GAIN
STAND_W_RAW
PHA_VAR_RAW
CAL_CONTROL
LINE_CYC_CNT
ENERGY_W_Z
ENERGY_W_L
ENERGY_VAR
PHA_W_GLSB
PHA_W_RAW
PHA_W_GAIN
PHA_W_OFF
PHA_DELAY
ENERGY_W
MODE1DEF
INTERNAL REGISTER SUMMARY
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
LINE_CYC
PHA_VAR
STATUS1
Reserved
Reserved
Reserved
PERIOD
MODE1
CFNUM
PHA_W
CFDEN
Name
End
Bits
272
16
16
16
16
16
16
16
16
48
32
48
32
16
32
64
64
48
32
16
64
64
32
16
16
32
16
16
16
16
16
16
32
16
16
16
48
Calculation and Register Description
—
8
8
8
8
8
8
8
R/W
R/W Configuration register for operating mode of the meter
R/W Configuration register for calibration control
R/W 2
R/W Phase A delay (delay between voltage and current, voltage is time shifted)
R/W Active power offset, Phase A
R/W Active power gain adjust for Phase A, for CF matching
R/W Active power gain adjust for Phase A, to produce X W/LSB
R/W Not implemented
R/W Not implemented
R/W Not implemented
R/W Not implemented
R/W Not implemented
R/W Defines CF pulse width from 0 to 255 * 1.25 ms for 50 Hz. For 60 Hz line 0
R/W CF Calibration Pulse correction factor
R/W Power Up Configuration Register
R/W Status of Phase A Calibration
R/W Standard Phase Active Power Reading (place holder register used during
R/W CF Calibration Pulse correction factor
—
—
—
—
—
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reserved
Status Register
Reserved
Counter for number of line cycles
Reserved
Reserved
Raw phase A active power
Final Phase A active power, units in watts (W)
Not implemented
Not implemented
Not implemented
Period register
Total active energy accumulated
Total active energy accumulated since last read of this register
Total energy accumulated over last LINE_CYC line cycles
Not implemented
Not implemented
Not implemented
Not implemented
Reserved
Reserved
Reserved
End of PIC18F85J90 RAM
Reserved
to 255 * 1.042 ms
Reserved
Reserved
calibration for gain matching)
Reserved
nd
number of line cycles to be used during energy accumulation
Description
DS51884A-page 19