PIC18F97J60T-I/PT Microchip Technology, PIC18F97J60T-I/PT Datasheet - Page 244

• Manufacturer Part Number: PIC18F97J60T-I/PT
• Description: IC PIC MCU FLASH 64KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60T-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3808Byte
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
18.6
The Ethernet module does not support Automatic
Duplex mode negotiation. If it is connected to an auto-
matic duplex negotiation enabled network switch or
Ethernet controller, the module will be detected as a
half-duplex device. To communicate in full duplex, the
module and the remote node (switch, router or Ethernet
controller) must be manually configured for full-duplex
operation.
18.6.1
The Ethernet module operates in Half-Duplex mode
when the FULDPX (MACON3<0>) and PDPXMD
(PHCON1<8>) bits are cleared (= 0). If only one of
these two bits is set, the module will be in an indetermi-
nate state and not function correctly. Since switching
between Full and Half-Duplex modes may result in this
indeterminate state, it is recommended that the appli-
cation not transmit any packets (maintain the TXRTS
bit clear), and disable packet reception (maintain the
RXEN bit clear) during this period.
In Half-Duplex mode, only one Ethernet controller may
be transmitting on the physical medium at any time. If
the application requests a packet to be transmitted by
setting the TXRTS bit while another Ethernet controller
is already transmitting, the Ethernet module will delay,
waiting for the remote transmitter to stop. When it
stops, the module will attempt to transmit its packet.
Should another Ethernet controller start transmitting at
approximately the same time, the data on the wire will
become corrupt and a collision will occur.
The hardware will handle this condition in one of two
ways. If the collision occurs before 64 bytes have been
transmitted, the following events occur:
1.
2.
3.
4.
DS39762C-page 242
the TXRTS bit remains set;
the transmit error interrupt does not occur;
a random exponential backoff delay elapses, as
defined by the IEEE 802.3 specification;
a new attempt to transmit the packet from the
beginning occurs. The application does not
need to intervene.
Duplex Mode Configuration and
Negotiation
HALF-DUPLEX OPERATION
Preliminary
If the number of retransmission attempts reaches 15 and
another collision occurs, the packet is aborted and the
TXRTS bit is cleared. The application will then be
responsible for taking appropriate action. The applica-
tion will be able to determine that the packet was aborted
instead of being successfully transmitted by reading the
TXABRT flag. For more information, see Section 18.5.2
“Transmitting Packets”.
If the collision occurs after 64 bytes have already been
transmitted, the packet is immediately aborted without
any retransmission attempts. Ordinarily, in IEEE 802.3
compliant networks which are properly configured, this
late collision will not occur. User intervention may be
required to correct the issue. This problem may occur
as a result of a full-duplex node attempting to transmit
on the half-duplex medium. Alternately, the module
may be attempting to operate in Half-Duplex mode
while it may be connected to a full-duplex network.
Excessively long cabling and network size may also be
a possible cause of late collisions.
18.6.2
The Ethernet module operates in Full-Duplex mode
when the FULDPX (MACON3<0>) and PDPXMD
(PHCON1<8>) bits are both set (= 1). If only one of
these two bits is clear, the module will be in an indeter-
minate state and not function correctly. Again, since
switching between Full and Half-Duplex modes may
result in this indeterminate state, it is recommended
that the application not transmit any packets and
should disable packet reception during this period.
In Full-Duplex mode, packets will be transmitted while
simultaneously packets may be received. Given this, it
is impossible to cause any collisions when transmitting
packets.
FULL-DUPLEX OPERATION
© 2007 Microchip Technology Inc.