PIC18F97J60T-I/PT Microchip Technology, PIC18F97J60T-I/PT Datasheet - Page 355
PIC18F97J60T-I/PT
Manufacturer Part Number
PIC18F97J60T-I/PT
Description
IC PIC MCU FLASH 64KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F97J60T-I/PT
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC18
No. Of I/o's
70
Ram Memory Size
3808Byte
Cpu Speed
41.667MHz
No. Of Timers
5
No. Of
RoHS Compliant
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F97J60T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F97J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPT PDF datasheet #7
- Current page: 355 of 476
- Download datasheet (9Mb)
24.2
For PIC18F97J60 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 24-1:
REGISTER 24-9:
TABLE 24-2:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
WDTPS3:WDTPS0
Name
All Device Resets
U-0
INTRC Oscillator
—
Watchdog Timer (WDT)
This bit has no effect if the Configuration bit, WDTEN, is enabled.
SWDTEN
CLRWDT
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Sleep
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
U-0
—
WDT BLOCK DIAGRAM
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit 6
Enable WDT
—
—
W = Writable bit
‘1’ = Bit is set
U-0
—
WDT Counter
Bit 5
CM
—
÷128
INTRC Control
4
U-0
Bit 4
—
Preliminary
Programmable Postscaler
RI
—
1:1 to 1:32,768
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
PIC18F97J60 FAMILY
TO
—
24.2.1
The WDTCON register (Register 24-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
U-0
—
Note 1: The CLRWDT and SLEEP instructions
WDT
2: When a CLRWDT instruction is executed,
Bit 2
PD
—
(1)
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
U-0
—
Bit 1
POR
—
x = Bit is unknown
SWDTEN
U-0
Bit 0
BOR
—
DS39762C-page 353
Wake-up from
Power-Managed
Modes
WDT
Reset
Reset Values
SWDTEN
on Page:
R/W-0
60
60
bit 0
(1)
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