ATMEGA329P-20AN Atmel, ATMEGA329P-20AN Datasheet - Page 144

• Manufacturer Part Number: ATMEGA329P-20AN
• Description: IC MCU AVR 32K 20MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20AN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5.1
17.5.2
8021G–AVR–03/11
Force Output Compare
Compare Match Blocking by TCNT2 Write
Generator for handling the special cases of the extreme values in some modes of operation.
See
Figure 17-3
Figure 17-3. Output Compare Unit, Block Diagram
The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is
disabled the CPU will access the OCR2A directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the
OCF2A Flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare
match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or
toggled).
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial-
ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
”Modes of Operation” on page
shows a block diagram of the Output Compare unit.
bottom
FOCn
top
OCRnx
146.
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMnX1:0
ATmega329P/3290P
TCNTn
OCFnx (Int.Req.)
OCnx
144