PIC18F65K90-I/MRRSL Microchip Technology, PIC18F65K90-I/MRRSL Datasheet - Page 317
![MCU PIC 32K FLASH MEM XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/MRRSL
Manufacturer Part Number
PIC18F65K90-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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21.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which greatly expands the number of
addresses Acknowledged.
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking the SSPxBUF.
The PIC18F87K90 family of devices is capable of using
two different Address Masking modes in I
operation: 5-Bit Address Masking and 7-Bit Address
Masking. The Masking mode is selected at device
configuration using the MSSPMSK Configuration bit.
The default device configuration is 7-Bit Address
Masking.
Both Masking modes, in turn, support address masking
of 7-bit and 10-bit addresses. The combination of
Masking modes and addresses provide different
ranges of Acknowledgable addresses for each
combination.
While both Masking modes function in roughly the
same manner, the way they use address masks are
different.
21.4.3.3
As the name implies, 5-Bit Address Masking mode
uses an address mask of up to 5 bits to create a range
of addresses to be Acknowledged, using bits, 5 through
1, of the incoming address. This allows the module to
EXAMPLE 21-2:
2010 Microchip Technology Inc.
7-Bit Addressing:
10-Bit Addressing:
2
C slave behaves the same way whether address
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPxADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
Address Masking Modes
5-Bit Address Masking Mode
ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE
2
C slave can Acknowledge
2
C slave
Preliminary
PIC18F87K90 FAMILY
Acknowledge up to 31 addresses when using 7-bit
addressing, or 63 addresses with 10-bit addressing
(see Example 21-2). This Masking mode is selected
when the MSSPMSK Configuration bit is programmed
(‘0’).
The address mask in this mode is stored in the
SSPxCON2 register, which stops functioning as a
control register in I
7-Bit Address Masking mode, address mask bits,
ADMSK<5:1> (SSPxCON2<5:1>), mask the corre-
sponding address bits in the SSPxADD register. For
any ADMSK bits that are set (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPxADD<n> = x).
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have
an active address mask.
In 10-Bit Address Masking mode, bits, ADMSK<5:2>,
mask the corresponding address bits in the SSPxADD
register. In addition, ADMSK1 simultaneously masks
the two LSbs of the address (SSPxADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the cor-
responding address bit is ignored (SPxADD<n> = x).
Also note, that although in 10-Bit Address Masking
mode, the upper address bits reuse part of the
SSPxADD register bits. The address mask bits do not
interact with those bits; they only affect the lower
address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
2
C Slave mode (Register 21-6). In
DS39957B-page 317
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