PIC18F65K90-I/MRRSL Microchip Technology, PIC18F65K90-I/MRRSL Datasheet - Page 444
![MCU PIC 32K FLASH MEM XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/MRRSL
Manufacturer Part Number
PIC18F65K90-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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multiplexer selects the clock source selected by the
PIC18F87K90 FAMILY
FIGURE 28-5:
28.5.3
By entering a power-managed mode, the clock
OSCCON register. Fail-Safe Monitoring of the power-
managed clock source resumes in the power-managed
mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1 ), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.
28.5.4
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
DS39957B-page 444
Note:
Sample Clock
CM Output
FSCM INTERRUPTS IN
POWER-MANAGED MODES
POR OR WAKE FROM SLEEP
OSCFIF
Device
Output
Clock
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
(Q)
FSCM TIMING DIAGRAM
CM Test
Preliminary
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FCSM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically config-
ured as the device clock and functions until the primary
clock is stable (when the OST and PLL timers have
timed out).
This is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTOSC returns to its role
as the FSCM source.
As noted in Section 28.4.1 “Special Considerations
for Using Two-Speed Start-up” , it is also possible to
select another clock configuration and enter an
alternate power-managed mode while waiting for the
primary clock to become stable. When the new power-
managed mode is selected, the primary clock is
disabled.
Note:
CM Test
Oscillator
Failure
The same logic that prevents false oscilla-
tor failure interrupts on POR, or wake from
Sleep, also prevents the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
2010 Microchip Technology Inc.
Detected
Failure
CM Test
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