ATMEGA3290PV-10AUR Atmel, ATMEGA3290PV-10AUR Datasheet - Page 198

• Manufacturer Part Number: ATMEGA3290PV-10AUR
• Description: MCU AVR 32K FLASH 10MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3290PV-10AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20. USI – Universal Serial Interface
20.1
20.2
8021G–AVR–03/11
Features
Overview
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The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown on Figure 20-1. For the actual placement of I/O
pins, refer to
page 3
device-specific I/O Register and bit locations are listed in the
206.
Figure 20-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wake up from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
”MLF/ Pinout ATmega329P” on page 2
USIDR
USICR
USISR
2
4-bit Counter
3
2
1
0
3
2
1
0
D Q
LE
[1]
TIM0 COMP
0
1
and
ATmega329P/3290P
Two-wire Clock
Control Unit
”TQFP / Pinout ATmega3290P” on
”Register Description” on page
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
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