PIC16LC65B-04/PQ Microchip Technology, PIC16LC65B-04/PQ Datasheet - Page 94

• Manufacturer Part Number: PIC16LC65B-04/PQ
• Description: IC MCU OTP 4KX14 PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65B-04/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• Data Rom Size: 192 B
• Height: 2 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3.65 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC16C63A/65B/73B/74B
FIGURE 13-5:
13.5.1
The external interrupt on RB0/INT pin is edge trig-
gered: either rising if bit INTEDG (OPTION_REG<6>)
is set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 13.8 for details on SLEEP mode.
13.5.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (see Section 6.0).
DS30605C-page 94
The following table shows which devices have which interrupts.
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
PSPIF
PSPIE
CCP2IF
CCP2IE
Device
ADIF
ADIE
INT INTERRUPT
TMR0 INTERRUPT
TMR1IF
TMR1IE
T0IF
Yes
Yes
Yes
Yes
RCIF
RCIE
TMR2IF
TMR2IE
00h) in the TMR0 register will set
INTERRUPT LOGIC
INTF
Yes
Yes
Yes
Yes
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
RBIF
Yes
Yes
Yes
Yes
PSPIF
Yes
Yes
–
–
ADIF
Yes
Yes
–
–
RCIF
Yes
Yes
Yes
Yes
TXIF
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
Yes
Yes
Yes
Yes
13.5.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note:
SSPIF
Yes
Yes
Yes
Yes
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
PORTB INTERRUPT-ON-CHANGE
CCP1IF
Yes
Yes
Yes
Yes
TMR2IF
Yes
Yes
Yes
Yes
2000 Microchip Technology Inc.
Wake-up (If in SLEEP mode)
TMR1IF
Yes
Yes
Yes
Yes
Interrupt to CPU
CCP2IF
Yes
Yes
Yes
Yes