ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 376
ATMEGA128A-AUR
Manufacturer Part Number
ATMEGA128A-AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8151H–AVR–02/11
4. Stabilizing time needed when changing OSCCAL Register
5. IDCODE masks data from TDI input
6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
NOP
NOP
NOP
NOP
SEI
After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-
ister, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this
errata.
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-
ister triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
– If ATmega128A is the only device in the scan chain, the problem is not visible.
– Select the Device ID Register of the ATmega128A by issuing the IDCODE
– If the Device IDs of all devices in the boundary scan chain must be captured
instruction or by entering the Test-Logic-Reset state of the TAP controller to read out
the contents of its Device ID Register and possibly data from succeeding devices of
the scan chain. Issue the BYPASS instruction to the ATmega128A while reading the
Device ID Registers of preceding devices of the boundary scan chain.
simultaneously, the ATmega128A must be the fist device in the chain.
; no operation
; no operation
; no operation
; no operation
; set global interrupt enable
ATmega128A
376
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