PIC18LF47J53-I/ML Microchip Technology, PIC18LF47J53-I/ML Datasheet - Page 372

• Manufacturer Part Number: PIC18LF47J53-I/ML
• Description: IC PIC MCU 128KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF47J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F47J53 FAMILY
The analog reference voltage is software select-
able to either the device’s positive and negative
supply voltage (AV
level
RA2/AN2/C2INB/C1IND/C3INB/V
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
FIGURE 22-1:
DS39964B-page 372
Note 1: Channels, AN5, AN6 and AN7, are not available on 28-pin devices.
on
Converter
2: I/O pins have diode protection to V
10/12-Bit
A/D
the
Reference
Voltage
DD
RA3/AN3/C1INB/V
A/D BLOCK DIAGRAM
and AV
SS
V
V
REF
), or the voltage
REF
REF
-/CV
+
-
(Input Voltage)
REF
REF
VCFG<1:0>
+
V
DD
AIN
and V
pins.
and
Preliminary
SS
V
.
DD
V
(2)
SS (2)
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF, is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset (POR). These registers will contain
unknown data after a POR.
Figure 22-1 provides the block diagram of the A/D
module.
CHS<3:0>
1001
1000
1111
1110
1100
1011
1010
0111
0110
0101
0100
0011
0010
0001
0000
 2010 Microchip Technology Inc.
AN9
AN8
V
V
AN12
AN11
AN10
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
BG
DDCORE
(1)
(1)
(1)
/V
CAP