DSPIC33FJ64GP204-I/PT Microchip Technology, DSPIC33FJ64GP204-I/PT Datasheet - Page 82

• Manufacturer Part Number: DSPIC33FJ64GP204-I/PT
• Description: IC DSPIC MCU/DSP 64K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP204-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Embedded Interface Type: ECAN, I2C, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 64KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.1
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
TABLE 6-1:
DS70292E-page 82
FRC, FRCDIV16,
FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
SOSC
LPRC
Note 1:
Oscillator Mode
2:
3:
System Reset
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal), if PLL is enabled.
= Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
Startup Delay
Oscillator
T
T
T
T
T
T
T
T
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
—
—
OST
= 32 ms for a 32 kHz crystal.
Oscillator Startup
Timer
T
T
T
T
T
OST
OST
OST
OST
OST
—
—
—
—
—
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure
6-2.
PLL Lock Time
T
T
T
T
LOCK
LOCK
LOCK
LOCK
—
—
—
—
—
—
© 2011 Microchip Technology Inc.
T
T
OSCD
OSCD
OST
T
T
T
T
OSCD
Total Delay
= 102.4 μs for a
OSCD
OSCD
OSCD
+ T
+ T
T
T
T
OSCD
OSCD
LOCK
OST
OST
—
+ T
+ T
+ T
+ T
LOCK
+ T
+ T
OST
OST
OST
LOCK
LOCK