PIC16F77-E/PT Microchip Technology, PIC16F77-E/PT Datasheet - Page 284
![IC MCU FLASH 8KX14 A/D 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16F77-E/PT
Manufacturer Part Number
PIC16F77-E/PT
Description
IC MCU FLASH 8KX14 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F77-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16F77E/PT
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 284 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
Register 17-3:
DS31017A-page 17-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: SSP Control Register2
bit 7
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (In I
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (In I
1 = Enables Receive mode for I
0 = Receive idle
PEN: Stop Condition Enable bit (In I
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
RSEN: Repeated Start Condition Enabled bit (In I
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
SEN: Start Condition Enabled bit (In I
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
GCEN
R/W-0
Note:
Note:
Note:
Note:
Note:
Automatically cleared by hardware.
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
ACKSTAT
R/W-0
2
2
2
2
2
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
W = Writable bit
ACKDT
R/W-0
Preliminary
2
2
C master mode only)
C
2
2
2
C master mode only)
C master mode only)
C slave mode only)
2
C master mode only)
ACKEN
R/W-0
2
C master mode only)
2
2
C master mode only)
- n = Value at POR reset
C master mode only)
RCEN
R/W-0
R/W-0
PEN
1997 Microchip Technology Inc.
R/W-0
RSEN
bit 0
R/W-0
SEN
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