AT89C51RC2-SLSUM Atmel, AT89C51RC2-SLSUM Datasheet - Page 89

• Manufacturer Part Number: AT89C51RC2-SLSUM
• Description: IC 8051 MCU FLASH 32K 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RC2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Cpu Family: 89C
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 60MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4180E–8051–10/06
Table 67. Default Values
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 67 and Table 69.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 68. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 69.
Mnemonic
Number
Bit
SBV
HSB
BSB
SSB
1-0
7
-
7
6
5
4
3
2
Mnemonic Description
Definition
Software Boot Vector
Hardware security Byte
Boot Status Byte
Software Security Byte
Copy of the Manufacturer Code
Copy of the Device ID #1: Family Code
Copy of the Device ID #2: memories
size and type
Copy of the Device ID #3: name and
revision
LB1-0
Bit
6
-
-
-
-
-
-
-
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
User Memory Lock Bits
see Table 69
5
-
4
-
3
-
Default value
101x 1011b
AT89C51RB2/RC2
0FFh
FCh
D7h
FBh
EFh
FFh
58h
F7h
FFh
2
-
Description
ATMEL
C51 X2, Electrically Erasable
AT89C51RB2/RC2 32KB
AT89C51RB2/RC2 16 KB
AT89C51RB2/RC2 32KB,
Revision 0
AT89C51RB2/RC2 16 KB,
Revision 0
LB1
1
LB0
0
89