ATMEGA8HVA-4TU Atmel, ATMEGA8HVA-4TU Datasheet - Page 91
![MCU AVR 8K FLASH 4MHZ 28-TSOP](/photos/7/21/72191/313-28-tsop_sml.jpg)
ATMEGA8HVA-4TU
Manufacturer Part Number
ATMEGA8HVA-4TU
Description
MCU AVR 8K FLASH 4MHZ 28-TSOP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA8HVA-4TU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
28-TSOP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.10.2
17.10.3
17.10.4
8024A–AVR–04/08
TCNTnL – Timer/Counter n Register Low Byte
TCNTnH – Timer/Counter n Register High Byte
OCRnA – Timer/Counter n Output Compare Register A
The Timer/Counter Register TCNTnL gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) the Com-
pare Match on the following timer clock. Modifying the counter (TCNTnL) while the counter is
running, introduces a risk of missing a Compare Match between TCNTnL and the OCRnx Regis-
ters. In 16-bit mode the TCNTnL register contains the lower part of the 16-bit Timer/Counter n
Register.
When 16-bit mode is selected (the TCWn bit is set to one) the Timer/Counter Register TCNTnH
combined to the Timer/Counter Register TCNTnL gives direct access, both for read and write
operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers. See
mode, this register is accessable for both reading and writing, but will not be updated by the
counter.
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNTnL). A match can be used to generate an Output Compare interrupt.
In 16-bit mode the OCRnA register contains the low byte of the 16-bit Output Compare Register.
To ensure that both the high and the low bytes are written simultaneously when the CPU writes
to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
This temporary register is shared by all the other 16-bit registers. See
16-bit Mode” on page
Note that the OCRnA is not writable in Input Capture mode.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
86.
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
”Accessing Registers in 16-bit Mode” on page
5
0
5
0
R/W
R/W
R/W
0
4
4
0
4
0
TCNTnL[7:0]
TCNTnH[7:0]
OCRnA[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
ATmega8HVA/16HVA
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
”Accessing Registers in
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
86. In 8-bit
TCNTnH
TCNTnL
OCRnA
91
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