AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet
AT91SAM7S321-AU
Specifications of AT91SAM7S321-AU
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AT91SAM7S321-AU Summary of contents
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... Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) – 32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane) – Single Cycle Access MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – ...
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... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs Supported • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ™ • ...
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... Configuration Summary of the AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 and AT91SAM7S32 The AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 and AT91SAM7S32 differ in memory size, peripheral set and package. the configuration of the six devices. Except for the AT91SAM7S32, all other AT91SAM7S devices are package and pinout compatible ...
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Block Diagram Figure 2-1. AT91SAM7S512/256/128/64/321 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
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Figure 2-2. AT91SAM7S32 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...
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Signal Description Table 3-1. Signal Description List Signal Name Function VDDIN Voltage and ADC Regulator Power Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
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Package and Pinout The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The AT91SAM7S32 is available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP and 64-pad QFN Package Outlines Figure 4-1 package. A ...
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LQFP and 64-pad QFN Pinout Table 4-1. AT91SAM7S512/256/128/64/321 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 ...
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LQFP and 48-pad QFN Package Outlines Figure 4-3 package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. AT91SAM7S32 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input ...
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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven ...
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I/O Line Drive Levels The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture • Two instruction sets • Three-stage pipeline architecture 7.2 Debug and Test Features • Integrated EmbeddedICE • Debug Unit • IEEE1149.1 JTAG Boundary-scan on ...
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Peripheral DMA Controller • Handles data transfer between peripherals and memories • Eleven channels: AT91SAM7S512/256/128/64/321 • Nine channels: AT91SAM7S32 • Low bus arbitration overhead • Next Pointer management for reducing interrupt latency requirements 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary – Prefetch ...
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Memories 8.1 AT91SAM7S512 • 512 Kbytes of Flash Memory, dual plane • 64 Kbytes of Fast SRAM 8.2 AT91SAM7S256 • 256 Kbytes of Flash Memory, single plane • 64 Kbytes of Fast SRAM 8.3 AT91SAM7S128 • 128 Kbytes of ...
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... AT91SAM7S64 • 64 Kbytes of Flash Memory, single plane • 16 Kbytes of Fast SRAM 8.5 AT91SAM7S321/32 • 32 Kbytes of Flash Memory, single plane • 8 Kbytes of Fast SRAM 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary – 512 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – ...
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Figure 8-1. AT91SAM7S512/256/128/64/321/32 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7S Series Preliminary 20 ...
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... The AT91SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. • The AT91SAM7S64 features one bank (single plane Kbytes of Flash. • The AT91SAM7S321/32 features one bank (single plane Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset and before the Remap Command ...
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... The Flash of the AT91SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The 32,768 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S512/256/128 contains a 256-byte write buffer, accessible through a 32-bit interface.. • ...
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Lock Regions 8.7.3.1 AT91SAM7S512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S512 contains 32 lock regions and each lock region contains 64 ...
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... AT91SAM7S321/32 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S321/32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt ...
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The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and ...
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Figure 9-1. System Controller Block Diagram (AT91SAM7S512/256/128/64/321) irq0-irq1 periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset periph_nreset proc_nreset cal gpnvm[0] en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset usb_suspend periph_nreset periph_clk[2] dbgu_rxd PA0-PA31 6175G–ATARM–22-Nov-06 AT91SAM7S ...
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Figure 9-2. System Controller Block Diagram (AT91SAM7S32) periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset periph_nreset proc_nreset cal gpnvm[0] en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] dbgu_rxd PA0-PA20 AT91SAM7S Series Preliminary 28 ...
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Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...
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Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources • 8-level Priority Controller • Vectoring • Protect Mode • Fast Forcing • General Interrupt ...
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... Chip ID is 0x270B0940 for AT91SAM7S256 (VERSION 0) – Chip ID is 0x270A0740 for AT91SAM7S128 (VERSION 0) – Chip ID is 0x27090540 for AT91SAM7S64 (VERSION 0) – Chip ID is 0x27080342 for AT91SAM7S321 (VERSION 0) – Chip ID is 0x27080340 for AT91SAM7S32 (VERSION 0) – Input change interrupt – Half a clock period glitch filter ...
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Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The aim of this controller is to select the Power Mode of the Voltage Regulator between Nor- mal Mode (bit 0 ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...
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Table 10-2. Peripheral Note: 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM7S Series features one PIO controller, PIOA, that ...
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PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (AT91SAM7S512/256/128/64/321) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...
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Table 10-4. Multiplexing on PIO Controller A (SAM7S32) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...
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Serial Peripheral Interface • Supports communication with external serial devices • Master or slave serial peripheral bus interface 10.6 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memories • One, two or three bytes for ...
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Test Modes 10.8 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length ...
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Independent channel programming 10.11 USB Device Port (Does not pertain to AT91SAM7S32) • USB V2.0 full-speed compliant, 12 Mbits per second. • Embedded USB V2.0 full-speed transceiver • Embedded 328-byte dual-port RAM for endpoints • Four endpoints • Suspend/resume ...
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ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM ing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, ...
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ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state ...
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Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR Registers are unbanked registers. This means that each of them refers to the same ...
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers ...
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Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC 11.2.6 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded ...
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Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 Table 11-3. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH ...
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Debug and Test Features 12.1 Description The AT91SAM7S Series Microcontrollers feature a number of complementary debug and test capabilities. A common JTAG/ICE (EmbeddedICE) port is used for standard debugging func- tions, such as downloading code and single-stepping through programs. ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 on page 48 face is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example AT91SAM7S Series Preliminary 48 shows a complete ...
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Test Environment Figure 12-3 on page 49 preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure ...
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Debug and Test Pin Description Table 12-1. Pin Name NRST TST TCK TDI TDO TMS JTAGSEL DRXD DTXD AT91SAM7S Series Preliminary 50 Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Clock ...
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... Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. Table 12-2. Chip Name AT91SAM7S32 AT91SAM7S321 AT91SAM7S64 AT91SAM7S128 AT91SAM7S256 AT91SAM7S512 6175G–ATARM–22-Nov-06 ...
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For further details on the Debug Unit, see the Debug Unit section. 12.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when ...
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Table 12-3. Bit Number 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary AT91SAM7Sxx JTAG Boundary Scan Register Pin Name 96 95 PA17/PGMD5/AD0 PA18/PGMD6/AD1 PA21/PGMD9 PA19/PGMD7/AD2 PA20/PGMD8/AD3 PA16/PGMD4 79 78 ...
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Table 12-3. Bit Number AT91SAM7S Series Preliminary 54 AT91SAM7Sxx JTAG Boundary Scan Register (Continued) Pin Name 63 62 PA24/PGMD12 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 46 ...
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Table 12-3. Bit Number Note: 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary AT91SAM7Sxx JTAG Boundary Scan Register (Continued) Pin Name 30 29 PA26/PGMD14 PA27/PGMD15 PA28 PA3 PA2 PA1/PGMEN1 ...
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... Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name AT91SAM7S32 AT91SAM7S321 AT91SAM7S64 AT91SAM7S128 AT91SAM7S256 AT91SAM7S512 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. Chip Name AT91SAM7S32 AT91SAM7S321 AT91SAM7S64 AT91SAM7S128 AT91SAM7S256 AT91SAM7S512 AT91SAM7S Series Preliminary PART NUMBER 13 ...
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Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
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Functional Description 13.3.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • ...
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NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in ...
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Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed ...
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User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR The NRST input signal is resynchronized with SLCK to insure proper behav- ior ...
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Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock ...
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Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the ...
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Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is ...
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Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed ...
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Figure 13-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM7S Series Preliminary 66 read RSTC_SR 2 cycle resynchronization 6175G–ATARM–22-Nov-06 ...
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Reset Controller (RSTC) User Interface Table 13-1. Reset Controller (RSTC) Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read/Write Reset Value - 0x0000_0000 ...
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Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets ...
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Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read/Write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the ...
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AT91SAM7S Series Preliminary 71 ...
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AT91SAM7S Series Preliminary 72 6175G–ATARM–22-Nov-06 ...
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Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface Table 14-1. Real-time Timer (RTT) Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR ...
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Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time ...
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Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.3 Real-time Timer Value Register Register Name: ...
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Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred ...
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Parallel Input Output Controller (PIO) 15.1 Overview The Parallel Input/Output Controller (PIO) manages fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I assigned to a function of an embedded ...
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Block Diagram Figure 15-1. Block Diagram AIC PMC Embedded Peripheral Embedded Peripheral Figure 15-2. Application Block Diagram Keyboard Driver Keyboard Driver AT91SAM7S Series Preliminary 80 PIO Controller PIO Interrupt PIO Clock Data, Enable peripheral IOs Data, ...
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Product Dependencies 15.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hard- ware-defined and ...
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Functional Description The PIO Controller features fully-programmable I/O lines. Most of the control logic asso- ciated to each I/O is represented in represents but one possible indexes. Figure 15-3. I/O Line Control ...
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Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull- up Disable Resistor). Writing in these registers results ...
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When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected ...
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Figure 15-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 PIO_ODSR PIO_PDSR 15.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg- ister ...
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Figure 15-5. Input Glitch Filter Timing MCK Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 PIO_PDSR if PIO_IFSR = 1 15.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input ...
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I/O Lines Programming Example The programing example as shown in configuration. • 4-bit output port on I/O lines (should be written in a single write operation), open-drain, with pull-up resistor • Four output signals on I/O ...
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User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control- ler User Interface registers. Each register is 32 bits wide parallel I/O line is not defined, ...
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Table 15-2. Register Mapping (Continued) Offset Register 0x0070 Peripheral A Select Register 0x0074 Peripheral B Select Register 0x0078 AB Status Register 0x007C to Reserved 0x009C 0x00A0 Output Write Enable 0x00A4 Output Write Disable 0x00A8 Output Write Status Register 0x00AC Reserved ...
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PIO Controller PIO Enable Register Name: PIO_PER Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: PIO Enable effect Enables the PIO ...
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PIO Controller PIO Status Register Name: PIO_PSR Access Type: Read-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O ...
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PIO Controller Output Disable Register Name: PIO_ODR Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Output Disable effect Disables the output ...
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PIO Controller Input Filter Enable Register Name: PIO_IFER Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Input Filter Enable effect Enables ...
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PIO Controller Input Filter Status Register Name: PIO_IFSR Access Type: Read-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Input Filer Status 0 = The input glitch filter is ...
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PIO Controller Clear Output Data Register Name: PIO_CODR Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Set Output Data effect Clears ...
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PIO Controller Pin Data Status Register Name: PIO_PDSR Access Type: Read-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Output Data Status 0 = The I/O line is at ...
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PIO Controller Interrupt Disable Register Name: PIO_IDR Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Input Change Interrupt Disable effect Disables ...
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PIO Controller Interrupt Status Register Name: PIO_ISR Access Type: Read-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Input Change Interrupt Status Input Change has been ...
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PIO Multi-driver Disable Register Name: PIO_MDDR Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Multi Drive Disable effect Disables Multi Drive ...
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PIO Pull Up Disable Register Name: PIO_PUDR Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Pull Up Disable effect Disables the ...
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PIO Pull Up Status Register Name: PIO_PUSR Access Type: Read-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Pull Up Status Pull Up resistor is enabled on ...
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PIO Peripheral B Select Register Name: PIO_BSR Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Peripheral B Select effect Assigns the ...
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PIO Output Write Enable Register Name: PIO_OWER Access Type: Write-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Output Write Enable effect Enables writing ...
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PIO Output Write Status Register Name: PIO_OWSR Access Type: Read-only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Output Write Status Writing PIO_ODSR does not affect the ...
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Periodic Interval Timer (PIT) 16.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 Block Diagram Figure 16-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 ...
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Periodic Interval Timer (PIT) User Interface Table 16-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7S Series Preliminary 108 Name Access PIT_MR ...
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Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read/Write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the ...
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Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the ...
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Watchdog Timer (WDT) 17.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 113 ...
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Watchdog Timer (WDT) User Interface Table 17-1. Watchdog Timer (WDT) Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register 17.4.1 Watchdog Timer Control Register Register Name: WDT_CR Access Type: Write-only – ...
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Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read/Write Once 31 30 – – WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...
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Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read ...
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Voltage Regulator Mode Controller (VREG) 18.1 Overview The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. ...
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Voltage Regulator Power Controller (VREG) User Interface Table 18-1. Voltage Regulator Power Controller Register Mapping Offset Register 0x60 Voltage Regulator Mode Register 18.2.1 Voltage Regulator Mode Register Register Name: VREG_MR Access Type: Read/Write 31 30 – – ...
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Memory Controller (MC) 19.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a simple bus arbiter, an address decoder, an ...
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Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters made up of: • A bus arbiter • An address decoder • An abort status • A misalignment detector • ...
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Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte ...
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Abort Status There are three reasons for an abort to occur: • access to an undefined address • an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of ...
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Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Memory Controller (MC) Register Mapping Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x0C-0x5C Reserved 0x60 EFC0 Configuration Registers 0x70 EFC1 ...
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MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x00 31 30 – – – – – – – – • RCB: Remap Command Bit 0: No effect. 1: This Command ...
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MC Abort Status Register Register Name: MC_ASR Access Type: Read-only Reset Value: 0x0 Offset: 0x04 31 30 – – – – – – – – • UNDADD: Undefined Address Abort Status 0: The ...
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MST1: ARM7TDMI Abort Source 0: The last aborted access was not due to the ARM7TDMI. 1: The last aborted access was due to the ARM7TDMI. • SVMST0: Saved PDC Abort Source 0: No abort due to the PDC occurred. ...
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... GPNVM assignment. The Embedded Flash size, the page size and the lock region organization are described in the product definition section. Table 20-1. Product Specific Lock and General-purpose NVM Bits AT91SAM7S512 AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 AT91SAM7S32 Denomination 6175G– ...
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Figure 20-1. Embedded Flash Memory Mapping 20.2.2 Read Operations An optimized controller manages embedded Flash reads. A system 32-bit buffers is added in order to start access at following address during the second read, thus increasing perfor- ...
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Figure 20-2. Code Read Optimization in Thumb Mode for FWS = 0 Master Clock ARM Request (16-bit) Code Fetch @Byte 0 @Byte 2 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Bytes 0-1 Note: When FWS is equal ...
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Figure 20-4. Code Read Optimization in Thumb Mode for FWS = 3 3 Wait State Cycles Master Clock ARM Request (16-bit) Code Fetch @Byte 0 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Note: When FWS is equal ...
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To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automati- cally cleared. Once the current command ...
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Figure 20-5. Command State Chart In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see Flash Mode Register” on page 20.2.4.1 Flash ...
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Figure 20-6. Example of Partial Page Programming: 32 bits wide ... 16 words ... 16 words ...
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Erase All operation is allowed only if there are no lock bits set. Thus least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written ...
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General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on the AT91SAM7S512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set ...
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When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the ...
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Embedded Flash Controller (EFC ) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7S512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register ...
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MC Flash Mode Register Register Name: MC_FMR Access Type: Read/Write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 30 – – – – NEBP – • FRDY: Flash Ready Interrupt Enable 0: Flash Ready ...
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FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest ...
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MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 – – – – • FCMD: Flash Command This field defines the Flash commands: FCMD ...
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PAGEN: Page Number Command Write Page Command Write Page and Lock Command Erase All Command Set/Clear Lock Bit Command Set/Clear General Purpose NVM Bit Command Set Security Bit Command Note: Depending on the command, all the possible unused bits ...
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MC Flash Status Register Register Name: MC_FSR Access Type: Read-only Offset: (EFC0) 0x68 Offset: (EFC1) 0x78 31 30 LOCKS15 LOCKS14 LOCKS13 23 22 LOCKS7 LOCKS6 15 14 – – – – • FRDY: Flash Ready Status 0: ...
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... LOCKS11 LOCKS11 LOCKS12 LOCKS12 LOCKS13 LOCKS13 LOCKS14 LOCKS14 LOCKS15 LOCKS15 Note: 1. The AT91SAM7S512 manages 16 lock bits on EF0 and 16 on EFC1 = 32. 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary AT91SAM7S321 AT91SAM7S32 8 16 LOCKS0 LOCKS0 LOCKS1 LOCKS1 LOCKS2 LOCKS2 LOCKS3 LOCKS3 LOCKS4 LOCKS4 LOCKS5 LOCKS5 ...
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AT91SAM7S Series Preliminary 144 6175G–ATARM–22-Nov-06 ...
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Fast Flash Programming Interface (FFPI) 21.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is ...
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Parallel Fast Flash Programming 21.2.1 Device Configuration In Fast Flash Programming Mode, the device specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 21-1. AT91SAM7S512/256/128/64/321 Parallel Programming ...
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Table 21-1. Signal Description List Signal Name Function VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. XIN This input can be tied to GND. In this ...
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Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 21-2. MODE[3:0] 0000 0001 0010 0011 0100 0101 Default When MODE is equal to CMDE, then a new command (strobbed on DATA[15:0] or DATA[7:0] ...
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Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. • Apply XIN clock within T • Wait for T • Start a read or write handshaking. Note: ...
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Figure 21-4. AT91SAM7S32 Parallel Programming Timing, Write Sequence Table 21-4. Write Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal ...
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Figure 21-6. AT91SAM7S32 Parallel Programming Timing, Read Sequence Table 21-5. Read Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Sets DATA signal in tristate 5 Clears NOE signal ...
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Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21-3 on page face running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining ...
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The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-7. Step ... n n+1 n+2 n+3 n+4 n+5 ... ...
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Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is pro- ...
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Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the ...
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Table 21-15. Write Command (Continued) Step n+4 n+5 ... 21.2.5.9 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-16. Get Version Command Step 1 2 AT91SAM7S Series Preliminary 156 Handshake Sequence MODE[3:0] ...
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Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a ...
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Table 21-17. Signal Description List (Continued) Signal Name Function TST Test Mode Select PGMEN0 Test Mode Select PGMEN1 Test Mode Select PGMEN2 Test Mode Select TCK JTAG TCK TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG ...
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Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these ...
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Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address ...
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Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands. 21.3.4.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase ...
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GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is returned, then the corresponding fuse bit is set. Table 21-25. Get General-purpose NVM Bit Command Read/Write Write Read 21.3.4.6 ...
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Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-29. Get Version Command Read/Write Write Read 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary DR Data GVE Version 163 ...
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AT91SAM7S Series Preliminary 164 6175G–ATARM–22-Nov-06 ...
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AT91SAM7 Boot Program 22.1 Description The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA DBGU serial ...
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Device Initialization with USB Initialization follows the steps described below: 1. FIQ initialization 1. Stack setup for ARM supervisor mode 2. Setup the Embedded Flash Controller 3. External Clock detection 4. Main oscillator frequency detection if no external clock ...
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SAM-BA Boot The SAM-BA boot principle is to: Figure 22-3. Auto Baudrate Flow Diagram 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary – Check if USB Device enumeration has occurred – Check if the AutoBaudrate sequence has succeeded (see Device Setup Character '0x80' ...
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Table 22-1. Command • Write commands: Write a byte (O), a halfword ( word (W) to the target. • Read commands: Read a byte (o), a halfword (h) ...
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SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. ...
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... The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. 22.5.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration send- ing requests to the device through the control endpoint ...
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... The remaining available sizes for the user codes are as follows: 57344 bytes for AT91SAM7S512, 57344 bytes for AT91SAM7S256, 24576 bytes for AT91SAM7S128, 8192 bytes for AT91SAM7S64, 2048 bytes for AT91SAM7S321 and AT91SAM7S32. • USB requirements: (Does not pertain to AT91SAM7S32) Table 22-4 ...
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AT91SAM7S Series Preliminary 172 6175G–ATARM–22-Nov-06 ...
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Peripheral DMA Controller (PDC) 23.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention ...
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Functional Description 23.3.1 Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset ...
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If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decre- mented after each ...
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Peripheral DMA Controller (PDC) User Interface Table 23-1. Register Mapping Register Offset 0x100 Receive Pointer Register 0x104 Receive Counter Register 0x108 Transmit Pointer Register 0x10C Transmit Counter Register 0x110 Receive Next Pointer Register 0x114 Receive Next Counter Register 0x118 ...
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PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: Read/Write • RXPTR: Receive Pointer Address Address of the next receive transfer. 23.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: ...
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PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: Read/Write • TXPTR: Transmit Pointer Address Address of the transmit buffer. 23.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read/Write ...
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PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: Read/Write • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when ...
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PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: Read/Write • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer ...
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PDC Transfer Control Register Register Name: PERIPH_PTCR - Access Type: Write only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable effect ...
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PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: Read-only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. ...
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Advanced Interrupt Controller (AIC) 24.1 Overview The Advanced Interrupt Controller (AIC 8-level priority, individually maskable, vectored interrupt controller, providing handling thirty-two interrupt sources designed to sub- stantially reduce the software and real-time ...
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Application Block Diagram Figure 24-2. Description of the Application Block 24.4 AIC Detailed Block Diagram Figure 24-3. AIC Detailed Block Diagram 24.5 I/O Line Description Table 24-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn AT91SAM7S Series Preliminary ...
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Product Dependencies 24.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control- lers. Depending on the features of the PIO controller used in the product, the pins must be programmed in ...
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Functional Description 24.7.1 Interrupt Source Control 24.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRC- TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal ...
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Each status referred to above can be used to optimize the interrupt handling of the systems. 24.7.1.5 Internal Interrupt Source Input Stage Figure 24-4. 24.7.1.6 External Interrupt Source Input Stage Figure 24-5. External Interrupt Source Input Stage Source i AIC_ISCR ...
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Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress ...
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External Interrupt Level Sensitive Source Figure 24-7. 24.7.2.3 Internal Interrupt Edge Triggered Source Figure 24-8. 24.7.2.4 Internal Interrupt Level Sensitive Source Figure 24-9. 6175G–ATARM–22-Nov-06 AT91SAM7S Series Preliminary External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ ...
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Normal Interrupt 24.7.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources (except for those programmed in Fast Forcing). Each interrupt source ...
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LDR When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an ...
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Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re- assertion of the nIRQ to be taken into account by the core. This can happen if an inter- rupt with a higher priority than ...
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Fast Interrupt 24.7.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a ...
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When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- cally clearing the fast interrupt has been programmed to be ...
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Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled ...
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Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associ- ated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM ...
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An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) • An interrupt occurs just a few cycles ...
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Advanced Interrupt Controller (AIC) User Interface 24.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor ...
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AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Read/Write Reset Value: 0x0 31 30 – – – – – – – SRCTYPE • PRIOR: Priority Level Programs the priority level for all ...
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AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read/Write Reset Value: 0x0 • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for ...