AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 405

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6
32.6.1
Table 32-4.
32.6.2
Table 32-5.
Notes:
6175G–ATARM–22-Nov-06
Offset
0xC0
0xC4
Offset
0x00
0x40
0x80
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0xFC
Timer/Counter (TC) User Interface
1. Read-only if WAVE = 0
Global Register Mapping
Channel Memory Mapping
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
Timer/Counter (TC) Global Register Map
TC Channel Memory Map
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Reserved
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC
block. TC channels are controlled by the registers listed in
channel registers in
tioned in
Table 32-5
.
Table 32-5
is in relation to the offset of the corresponding channel as men-
TC_CMR
TC_CCR
TC_IMR
AT91SAM7S Series Preliminary
TC_IER
TC_IDR
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
TC_BCR
TC_BMR
Name
Name
–
See
See
See
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Access
Access
Table 32-5
Table 32-5
Table 32-5
Table 32-5
–
(1)
(1)
. The offset of each of the
Reset Value
Reset Value
–
0
–
–
0
0
0
0
0
–
–
0
–
–
0
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