PIC16LC74B-04/L Microchip Technology, PIC16LC74B-04/L Datasheet - Page 22

• Manufacturer Part Number: PIC16LC74B-04/L
• Description: IC MCU OTP 4KX14 A/D PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC74B-04/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16C63A/65B/73B/74B
4.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 4-4:
DS30605C-page 22
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1 REGISTER (ADDRESS 8Ch)
Legend:
R = Readable bit
-n = Value at POR
bit 7
PSPIE
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
ADIE
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented; always
PSPIE
R/W-0
(2)
2: PIC16C63A/65B devices do not have an A/D implemented; always maintain this bit
(1)
(1)
: A/D Converter Interrupt Enable bit
: Parallel Slave Port Read/Write Interrupt Enable bit
maintain this bit clear.
clear.
ADIE
R/W-0
(2)
R/W-0
RCIE
W = Writable bit
’1’ = Bit is set
R/W-0
TXIE
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
SSPIE
CCP1IE
R/W-0
2000 Microchip Technology Inc.
x = Bit is unknown
TMR2IE
R/W-0
TMR1IE
R/W-0
bit 0