ATMEGA325-16AU Atmel, ATMEGA325-16AU Datasheet - Page 359

• Manufacturer Part Number: ATMEGA325-16AU
• Description: IC AVR MCU 32K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 54
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Package: 64TQFP
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2570M–AVR–04/11
23 JTAG Interface and On-chip Debug System ..................................... 218
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 224
25 Boot Loader Support – Read-While-Write Self-Programming ......... 251
22.4
22.5
22.6
22.7
22.8
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
Prescaling and Conversion Timing ................................................................204
Changing Channel or Reference Selection ...................................................206
ADC Noise Canceler .....................................................................................207
ADC Conversion Result .................................................................................211
Register Description ......................................................................................213
Features ........................................................................................................218
Overview ........................................................................................................218
TAP – Test Access Port ................................................................................218
TAP Controller ...............................................................................................220
Using the Boundary-scan Chain ....................................................................221
Using the On-chip Debug System .................................................................221
On-chip Debug Specific JTAG Instructions ...................................................222
Using the JTAG Programming Capabilities ...................................................223
Bibliography ...................................................................................................223
Register Description ......................................................................................223
Features ........................................................................................................224
System Overview ...........................................................................................224
Data Registers ...............................................................................................224
Boundary-scan Specific JTAG Instructions ...................................................226
Boundary-scan Related Register in I/O Memory ...........................................227
Boundary-scan Chain ....................................................................................228
Boundary-scan Order ....................................................................................237
Boundary-scan Description Language Files ..................................................250
Features ........................................................................................................251
Overview ........................................................................................................251
Application and Boot Loader Flash Sections .................................................251
Read-While-Write and No Read-While-Write Flash Sections ........................252
Boot Loader Lock Bits ...................................................................................254
Entering the Boot Loader Program ................................................................255
Addressing the Flash During Self-Programming ...........................................256
Self-Programming the Flash ..........................................................................257
Register Description ......................................................................................263
ATmega325/3250/645/6450
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